Single-Ended and Differential Ka-Band BiCMOS Phased Array Front-Ends

Min, Byung-Wook; Rebeiz, Gabriel M.

doi:10.1109/jssc.2008.2004336

Cited by 186 publications

(77 citation statements)

References 22 publications

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“…where N is number of phase shifting states, Ái is the phase error corresponding to the ith ideal phase value, and A Ái is the value of the difference between the ith insertion gain and the average insertion gain in all phase-states in dB-scale [7]. The RMS phase error is less than 1.7°over 20-45 GHz as shown in Fig.…”

Section: Rms Phase Errormentioning

confidence: 96%

“…The phase shifter is one of the most critical building blocks in phased array front end. Switched-type passive phase shifter [4,5,6,7] has high linearity, but suffers from high insertion loss in silicon process and consumes large chip area to achieve high phase resolution. Active phase shifter [8,9,10,11,12,13] applying vector summing method provides high phase resolution and compact size.…”

Section: Introductionmentioning

confidence: 99%

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A 6-bit 38 GHz SiGe BiCMOS phase shifter for 5G phased array communications

Wang

Liu

et al. 2017

IEICE Electron. Express

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This paper presents a 6-bit 38 GHz vector-summing phase shifter developed for 5G phased array communications. A linear gain adjustment VGA with modified gain control method is presented and is used in phase shifter for vectors weighting. Combined with a degenerated-Q quadrature all-pass filter (QAF) for accurate I/Q generation, high phase resolution is achieved with easy control and compact size. Fabricated in 0.13 um SiGe BiCMOS process, the phase shifter has a measured average insertion loss of 5.7 dB at 38 GHz center frequency, with −3 dB bandwidth of 12 GHz. The RMS phase and gain errors are less than 1.7°and 1.5 dB respectively across 20-45 GHz frequency range over 64 phase states. The chip has a compact core size of 373 um × 311 um and it consumes 11.2 mA from 3 V supply.

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Section: Rms Phase Errormentioning

confidence: 96%

Section: Introductionmentioning

confidence: 99%

A 6-bit 38 GHz SiGe BiCMOS phase shifter for 5G phased array communications

Wang

Liu

et al. 2017

IEICE Electron. Express

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“…The CPW input and output pad loss is included in the measurements and is 0.2 dB per pad at 35 GHz [23]. The only control inputs applied to the chips are supply voltages (analog and digital), address bits (2 bits for the four-element array), data bits (5 bit) and enabling clock signals to load the phase shifter data into the registers (four-element chip).…”

Section: Measurementsmentioning

confidence: 99%

Single and Four-Element $Ka$-Band Transmit/Receive Phased-Array Silicon RFICs With 5-bit Amplitude and Phase Control

Kang

Kim

Min

et al. 2009

IEEE Trans. Microwave Theory Techn.

139

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band SiGe BiCMOS single-and four-element phased arrays capable of both transmit and receive operation with 5-bit phase and amplitude control are presented. The design is based on the All-RF architecture with RF phase shifters and attenuators, and a 4:1 passive power combining/dividing network. The four-element array results in an average gain of 0 dB per channel and a noise figure of 9.0 dB, and is designed to be placed behind III-V T/R modules. The rms phase error is 5 6 (5-bit operation) and12 5 (4-bit operation) over a 2 or 5 GHz instantaneous bandwidth, respectively, centered at around 36.5 GHz. In the receive mode, the input P1dB is 16 dBm per channel (IIP3 of 5.9 dBm), and in the transmit mode, the output P1dB is +4-5 dBm, all at 35-36 GHz. The measured isolation between the channels is better than 30 dB. The array maintained excellent phase characteristics up to 100 C with no change in the rms phase error. Also, ten different four-element phased arrays were tested (40 channels) and result in an rms gain variation of 0.5 dB at 34-39 GHz. The four-element array consumes 171 and 142 mW in the Tx and Rx modes from 1.8 V, and occupies an area of 2.0 2.02 mm 2 . To our knowledge, this is the smallest and lowest power consumption on-chip -band phased-array to-date.Index Terms-Phase shifter, phased array, SiGe BiCMOS, T/R module, variable gain amplifier.

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“…ence. In particular, the maximum rms amplitude error exceeds 1 dB beyond 70 and shows the worst value, 2.3 dB, at a 90 phase difference; [6] is referred to in designing a single transistor switch. The details of the parameter are listed in Fig.…”

Section: Introductionmentioning

confidence: 99%

A Highly Integrated 1-Bit Phase Shifter Based on High-Pass/Low-Pass Structure

Song

Yoon

Park

2015

IEEE Microw. Wireless Compon. Lett.

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This letter presents a highly integrated 1-bit 90 phase shifter based on high-pass/low-pass structure for 60 GHz beamforming applications using a standard 65 nm CMOS process. In order to overcome the limitation of the conventional low-pass only phase shifter, the combination of high-pass/low-pass network was utilized as a 1-bit phase shifter. By integrating a high pass network into the low-pass network with low loss single-pole single throw (SPST) switches that adapt a resistive body floating technique, the proposed phase shifter achieves average 5 dB IL and less than dB of insertion loss flatness and 1 dB rms amplitude error over the whole band in a small chip area of 0.16 mm including pads.

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Single-Ended and Differential Ka-Band BiCMOS Phased Array Front-Ends

Cited by 186 publications

References 22 publications

A 6-bit 38 GHz SiGe BiCMOS phase shifter for 5G phased array communications

A 6-bit 38 GHz SiGe BiCMOS phase shifter for 5G phased array communications

Single and Four-Element $Ka$-Band Transmit/Receive Phased-Array Silicon RFICs With 5-bit Amplitude and Phase Control

A Highly Integrated 1-Bit Phase Shifter Based on High-Pass/Low-Pass Structure

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