Single-Crystalline Si-CMOS Circuit Fabrication on Polyethylene Terephthalate Substrate by Meniscus Force-Mediated Layer Transfer

Abstract

Single-crystalline silicon (sc-Si) complementary metal-oxide-semiconductor (CMOS) circuits were fabricated on a polyethylene terephthalate (PET) substrate using meniscus force-mediated layer transfer. The introduction of a two-step tapered SiO 2 structure formed using low-dose and high-energy pillar shaping ion implantation (I/I) and self-limited SiO 2 pillar etching were crucial for obtaining a high transfer yield of 99.86% and simultaneous transfer of both n-and p-channel sc-Si islands to the PET substrate. The fabricated MOS field-effect transistors exhibited a high field effect mobility of 603 cm 2 V −1 s −1 (n) and 172 cm 2 V −1 s −1 (p), respectively. The CMOS inverters exhibited clear input/output characteristics under a supply voltage of 2.0 V, and high-speed operation of a five-stage ring oscillator (RO) with an operating frequency of 14.6 MHz was realized. Moreover, the oscillation frequency of the RO transferred onto the PET was 3.5 times that of the non-transferred RO owing to the reduction in the parasitic capacitance.INDEX TERMS CMOS integrated circuits, CMOS process, flexible electronics, single-crystalline silicon layer transfer.

Development of high-yield layer transfer process of single-crystalline silicon thin films on plastic substrate and its application to multi-functional device integration

“…1(b)]. 25) A 400 nm BOX layer was etched by 10% hydrofluoric solution and uniform extra-fine tapered-shape SiO 2 pillars that supported the SOI islands in the mid-air cavity were formed as shown in Fig. 1(c).…”

“…3(b)]. Next, transfer of p/n-channel islands fabricated on SOI wafer 25) onto the FTO etched substrate was performed by the MLT technique [Fig. 3(c)].…”

“…23,24) In addition, we have demonstrated the fabrication and operation of high-performance CMOS circuits on PET substrates. 25) The MLT technique has achieved a transfer yield higher than 90%; however, a yield higher than 99.9% will be required for circuit fabrication. Therefore, it is important to improve the transfer yield and to get it as close as possible to 100% to fabricate integrated CMOS circuits.…”

2019 Index IEEE Journal of the Electron Devices Society Vol. 7

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