Single-chip 10.7 gb/s FEC codec LSI using time-multiplexed RS decoder

Seki, Kazuhiko; Mikami, K.; Baba, Masakazu; Shinohara, Nobuhiko; Suzuki, Shigenobu; Tezuka, Hiroyasu; Uchino, Shigenori; Okada, Nobuaki; Kakinuma, Y.; Katayama, A.

doi:10.1109/cicc.2001.929778

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

DOI: 10.1109/cicc.2001.929778

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Single-chip 10.7 gb/s FEC codec LSI using time-multiplexed RS decoder

Kazuhiko Seki

K. Mikami²,

Masakazu Baba³

et al.

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Cited by 8 publications

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Design for high-speed RS-codec based on Galois-field arithmetics

Choi

Kim²,

Kim³

APCC/MDMC '04. The 2004 Joint Conference of the 10th Asia-Pacific Conference on Communications and the 5th International Sympos

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Single-chip 10.7 gb/s FEC codec LSI using time-multiplexed RS decoder

Cited by 8 publications

References 1 publication

Design for high-speed RS-codec based on Galois-field arithmetics

Design for high-speed RS-codec based on Galois-field arithmetics

Single-chip FEC codec LSI using iterative CSOC decoder for 10 Gb/s long-haul optical transmission systems

Single-chip FEC codec using a concatenated BCH code for 10 Gb/s long-haul optical transmission systems

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