Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design

Olson, B.D.; Ball, D. R.; Warren, K.M.; Massengill, L.W.; Haddad, N.; Doyle, S.; McMorrow, D.

doi:10.1109/tns.2005.860684

Cited by 139 publications

(36 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…The parasitic bipolar effect is an additional effect that involves charge draining after a charged ion strike [12], [65], [66], [71], [74], [75]. Parasitic bipolar effect is the process where a PMOS transistor's junction between the P+ source and the N-well is forward biased, resulting in a P-N-P parasitic bipolar junction transistor through the PMOS substrate to be turned on.…”

Section: Parasitic Bipolar Based Equalization Mechanismmentioning

confidence: 99%

Single Event Transients and Pulse Quenching Effects in Bandgap Reference Topologies for Space Applications

Andreou

Javanainen

Rominski

et al. 2016

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

Abstract-An architectural performance comparison of bandgap voltage reference variants, designed in a 0.18 µm CMOS process, is performed with respect to single event transients. These are commonly induced in microelectronics in the space radiation environment. Heavy ion tests (Silicon, Krypton, Xenon) are used to explore the analog single-event transients and have revealed pulse quenching mechanisms in analogue circuits. The different topologies are compared, in terms of cross-section, pulse duration and pulse amplitude. The measured results, and the explanations behind the findings, reveal important guidelines for designing analog integrated circuits, which are intended for space applications. The paper includes an analysis on how pulse quenching occurs within the indispensable current mirror, which is used in every analog circuit.

show abstract

Section: Parasitic Bipolar Based Equalization Mechanismmentioning

confidence: 99%

Single Event Transients and Pulse Quenching Effects in Bandgap Reference Topologies for Space Applications

Andreou

Javanainen

Rominski

et al. 2016

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

show abstract

“…For the NMOS, the parasitic bipolar is not significant [12], and we choose β p = 1 for the NMOS. From the 3-D TCAD simulation results of [19,20], we choose β n = 2 for PMOS fabricated in 90 nm technology and β n = 3 for PMOS fabricated in 65 nm technology. …”

Section: -D Photocurrent Modelmentioning

confidence: 99%

Prediction of low-LET ion induced single event upset cross sections for advanced SRAM

Zhou

2013

Journal of Nuclear Science and Technology

View full text Add to dashboard Cite

This paper describes a simple circuit-level simulation-based approach to predict single event upset cross section induced by low-linear energy transfer (LET) ions for advanced bulk static random access memory (SRAM). A basic Simulation Program with Integrated Circuit Emphasis (SPICE) model with effective collection depth considered is developed for performing single event analysis quickly and efficiently. Through this circuit-level simulation model, radiation effects can be shown as the SPICE-simulated curve of LETs versus the corresponding affected distances, which are used for upset cross-section prediction. Furthermore, a fine-grain geometric model for cross-section prediction with fine sensitivity coefficient considered is utilized in the prediction. The calculated results based on this method are in good agreement with experimentally measured results reported for six-transistor SRAM fabricated in 90 nm and 65 nm process technologies.

show abstract

“…Meanwhile, the operation voltage reduces, less charge required for logic High level representing [1]. The advancement of technology has made SRAM cells more vulnerable to high energy ion strikes due to charge sharing and enhanced charge collection by parasitic bipolar effect [2]. Charge collection at sensitive nodes of SRAM cells may cause changes of stored data, namely SEU, which brings significant computation errors in subsequent operations.…”

Section: Introductionmentioning

confidence: 99%

A novel SEU hardened SRAM bit-cell design

Yang²,

Zhang

et al. 2017

IEICE Electron. Express

View full text Add to dashboard Cite

An improved single event upset (SEU) tolerant static random access memory (SRAM) bit-cell with differential read and write capability is proposed. SPICE simulation suggests a more than 1000 times improvement of the critical charge over the standard 6T SRAM cell. With the SEU robustness greatly enhanced at low area and electrical performance costs, the proposed cell is well suited to harsh radiation environment applications such as aerospace and high energy physics.

show abstract

Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design

Cited by 139 publications

References 14 publications

Single Event Transients and Pulse Quenching Effects in Bandgap Reference Topologies for Space Applications

Single Event Transients and Pulse Quenching Effects in Bandgap Reference Topologies for Space Applications

Prediction of low-LET ion induced single event upset cross sections for advanced SRAM

A novel SEU hardened SRAM bit-cell design

Contact Info

Product

Resources

About