Simultaneous scheduling, binding and floorplanning in high-level synthesis

Prabhakaran, P.; Banerjee, P.

doi:10.1109/icvd.1998.646645

Cited by 28 publications

(10 citation statements)

References 22 publications

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“…It is no longer possible to accurately predict the power consumption and performance of a design without first knowing enough about its floorplan to predict the structure of its interconnect. For this reason, a number of researchers have worked on interconnect-aware high-level synthesis algorithms [10][11][12][13]. These approaches typically use a loosely coupled independent floorplanner for physical estimation.…”

Section: Introductionmentioning

confidence: 99%

Incremental exploration of the combined physical and behavioral design space

Wang

Dick

et al. 2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly important factors such as the impact of interconnect on the area and power consumption of integrated circuits. Bringing physical information up into the logic level or even behavioral-level stages of system design is essential to solve this problem. In this paper, we present an incremental floorplanning high-level synthesis system. This system integrates high-level and physical design algorithms to concurrently improve a system's schedule, resource binding, and floorplan, thereby allowing the incremental exploration of the combined behavioral-level and physical-level design space. Compared with previous approaches that repeatedly call loosely coupled floorplanners for physical estimation, this approach has the benefit of efficiency, stability, and better quality of results. For designs containing functional units with non-unity aspect ratios, the average CPU time improved by 369 %, the area improved by 14.24 %, and power improved by 4 %.

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Section: Introductionmentioning

confidence: 99%

Incremental exploration of the combined physical and behavioral design space

Wang

Dick

et al. 2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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“…Similarly, a lot of techniques have already been proposed taking into account power consumption in high-level synthesis [4,5,6,7]. Just a few of these contributions also consider interconnect power [8,9,10]. For high-level interconnect length estimation the well known Rent's rule is often used [11].…”

Section: Introductionmentioning

confidence: 99%

Binding allocation and floorplanning in low power high-level synthesis

Stammermann¹,

Helms²,

Schulte³

et al. 2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is important that accurate physical information is used during high-level synthesis [1]. We propose a new power optimisation algorithm for RTlevel netlists. The optimisation performs simultaneously slicingtree structure-based floorplanning and functional unit binding and allocation. Since floorplanning, binding and allocation can use the information generated by the other step, the algorithm can greatly optimise the interconnect power. Compared to interconnect unaware power optimised circuits, it shows that interconnect power can be reduced by an average of 41.2 %, while reducing overall power by 24.1 % on an average. The functional unit power remains nearly unchanged. These optimisations are not achieved at the expense of area.

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“…Simultaneous scheduling and allocation [5], scheduling and binding [6], and scheduling and floorplanning [7] have been proposed. Prabhakaran et al in [8] proposed simultaneous scheduling, binding, and floorplanning. More recently, the bus binding problem has been integrated with scheduling to minimize power dissipation of the buses [9], [10].…”

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confidence: 99%

An Integrated Approach to Thermal Management in High-Level Synthesis

Mukherjee

Memik

2006

IEEE Trans. VLSI Syst.

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Abstract-Thermal effects are becoming an important factor in the design of integrated circuits due to the adverse impact of temperature on performance, reliability, leakage, and chip packaging costs. Making all phases of the design flow aware of this physical phenomenon helps in reaching faster design closure. In this paper, we present an integrated approach to thermal management in architectural synthesis. Our synthesis flow combines temperatureaware scheduling and binding based on feedback from thermal simulation. We show that our flow is effective in preventing hotspot formation and creating an even thermal profile of the resources. Our integrated thermal management technique on average reduces the peak temperature of the resources by 7.34 C when compared to a thermal unaware flow without increasing the number of resources across our set of benchmarks.

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Simultaneous scheduling, binding and floorplanning in high-level synthesis

Cited by 28 publications

References 22 publications

Incremental exploration of the combined physical and behavioral design space

Incremental exploration of the combined physical and behavioral design space

Binding allocation and floorplanning in low power high-level synthesis

An Integrated Approach to Thermal Management in High-Level Synthesis

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