Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty

Abstract

Technology scaling has not only magnified the effects of device process variations, but it has also precipitated the need for simultaneous optimization of several performance metrics. In this paper, we propose a novel gate sizing approach for multi-metric optimization of delay, power, and crosstalk noise. The algorithm is based on the concepts of mathematical programming, and models the process variation uncertainty considering spatial correlations. The approach identifies leakage power, dynamic power, and crosstalk noise as the objectives, and the optimized gate delays are kept as constraints. Initially, the deterministic upper and lower bounds of the objectives are identified, and during the final step, a crisp non-linear programming problem is formulated using these boundary values. The problem is solved using KNI-TRO, an interior-point based optimization solver. The proposed model maximizes the variation resistance, thus providing higher yield. ITC'99 benchmarks were used to test the proposed approach, and the results indicate that our algorithm identifies the solution points that are closest to the nominal bounds, while maintaining high timing yield.

Variation-aware multimetric optimization during gate sizing

“…Further, several mathematical programming techniques for delay optimization [Singh et al 2005;Chopra et al 2005], binning yield optimization [Davoodi and Srivastava 2006], and variation tolerance [Neiroukh and Song 2005] have also been proposed in recent years. In Ranganathan et al [2008], we have presented some initial results for multimetric gate sizing optimization using the fuzzy mathematical programming approach.…”