Simultaneous Extraction of Mobility Enhancement Factor and Threshold Voltage With Parasitic Resistances in Amorphous Oxide Semiconductor Thin-Film Transistors

Park, Ju Young; Kim, Haesung; Yoo, Han Bin; Ryu, Ji Hee; Han, Seung Hyeop; Bae, Jong-Ho; Choi, Sung-Jin; Kim, Dae Hwan; Kim, Dong Myong

doi:10.1109/ted.2023.3253468

IEEE Trans. Electron Devices

2023

DOI: 10.1109/ted.2023.3253468

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Simultaneous Extraction of Mobility Enhancement Factor and Threshold Voltage With Parasitic Resistances in Amorphous Oxide Semiconductor Thin-Film Transistors

Ju Young Park

Haesung Kim

Han Bin Yoo

et al.

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P‐1.15: Improving the Performance of IZO Transistor by Adding Buffer Layer

Xiong,

Shi,

xie

et al. 2024

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In this work, we studied the effect of the different thickness buffer layer on the electrical characteristics of InZnO (IZO) transistors. We found that when a 20nm layer of indium‐aluminum‐zinc oxide (IAZO) was added as the buffer layer between S/D electrodes and the active layer, the IZO transistor exhibited optimum electrical performance, with a high on/off drain current ratio of 2.61 ×107, the field‐effect mobility (μFE) of 15.75 cm2/Vs, the subthreshold swing (SS) of 129.85 mV/decade, and the turn‐on voltage (VON) of ‐0.4 V.

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P‐1.15: Improving the Performance of IZO Transistor by Adding Buffer Layer

Xiong,

Shi,

xie

et al. 2024

Symp Digest of Tech Papers

View full text Add to dashboard Cite

show abstract

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Simultaneous Extraction of Mobility Enhancement Factor and Threshold Voltage With Parasitic Resistances in Amorphous Oxide Semiconductor Thin-Film Transistors

Cited by 1 publication

References 28 publications

P‐1.15: Improving the Performance of IZO Transistor by Adding Buffer Layer

P‐1.15: Improving the Performance of IZO Transistor by Adding Buffer Layer

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