Simultaneous Driver And Wire Sizing For Performance And Power Optimization*

Cong, J.; Koh, Cheng-Kok

doi:10.1109/iccad.1994.629767

Cited by 46 publications

(95 citation statements)

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“…The simultaneous driver and wire sizing (SDWS) problem was studied in [35] and later generalized to simultaneous buffer and wire sizing (SBWS) in a buffered routing tree [36]. In both cases, the switch-resistor model is used for the driver and the Elmore delay model is used for the interconnects modeled as RC trees.…”

Section: F1 Simultaneous Device and Wire Sizingmentioning

confidence: 99%

Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

124

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I. INTERCONNECT TRENDS AND CHALLENGESThe driving force behind the impressive advancement of the VLSI circuit technology has been the rapid scaling of the feature size, i.e., the minimum dimension of the transistor. Table I lists the main characteristics of each technology generation in the NTRS. Such rapid scaling has two profound impacts. First, it enables much higher degree of on-chip integration. The number of transistors per chip will increase by more than 2 per generation to reach 800 millions in the© ¢ m technology. Second, it implies that the circuit performance will be increasingly determined by the interconnect performance. The interconnect design will play the most critical role in achieving the projected clock frequencies in the NTRS. This paper presents the trends and challenges of interconnect design in current and future technologies and discusses the available solutions.In order to better understand the significance of interconnect design in the future technology generations, we performed a number of experiments based on the interconnect parameters provided in the NTRS as shown in the bold face in Table II global interconnects, we also derived the interconnect parameters for the M4 layer,c which are also shown in Table II. Furthermore, we derived a set of device parameters as shown in Table III based on the data on processes and device in the NTRS. Using these sets of parameters, we carried out extensive simulations using HSPICE to quantitatively measure the interconnect performance and reliability in future technology generations and obtained the following results:(1) Interconnect delay is clearly the dominating factor in determincWe assume that the minimum width and spacing of M4 is 2.5 times those of M1. The aspect ratios 7 6 8 and 7 6 A @ are used to determine the metal thickness and the dielectric thickness for all layers. For M1, we assume that the substrate and M2 are the ground planes; and for M4, we assume that M3 and M5 are the ground planes. The total capacitance, including the area capacitance, fringing capacitance, and coupling capacitance components, are obtained using the 3D field solver FastCap [2]. Based on these assumptions, our capacitance values for M1 closely match those given in the NTRS.

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Section: F1 Simultaneous Device and Wire Sizingmentioning

confidence: 99%

Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

124

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“…These are all based on gate delay models that are compatible with geometric programming; see Kasamsetty et al (2000), Sakurai (1988), Sutherland et al (1999), Rubenstein et al (1983), and Abou-Seido et al (2004) for more on such models. Work on interconnect sizing (also addressed in this paper) includes Alpert et al (2001b), , Cong and Koh (1994), , Cong and Leung (1995), Cong and Pan (2002), Chen et al (2004), , Gao and Wong (1999), Kay and Pileggi (1998), Lee et al (2002), Lin and Pileggi (2001), and Sapatnekar (1996); simultaneous gate and wire sizing is considered in and Jiang et al (2000). In some of these papers, the authors develop custom methods for solving the resulting GPs instead of using general purpose interiorpoint methods (see, e.g., Chu and Wong 2001b, Ismail et al 2000, Young et al 2001.…”

Section: Sizing Optimization Via Geometric Programmingmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

151

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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“…T ransition density o r a v erage switching rate at dierent sites in a circuit is introduced in [11] as a quantity to measure the circuit activity, which can be used to estimate the average dynamic power consumption in a digital circuit. Previous research for low p o w er synthesis of digital circuits has focused on issues such as activity-driven technology decomposition and mapping [15], low p o w er state assignment [8], architectural transformation and reduction of power supply voltage [4], wire and driver sizing [5], and reversible and adiabatic computing [6]. In this paper we study the partitioning problem to exploit sleep mode operation for power minimization in digital circuits.…”

Section: Introductionmentioning

confidence: 99%

System partitioning to maximize sleep time

Farrahi¹,

Sarrafzadeh²

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

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Partitioning of a system to maximize exploitable sleep time for low-power synthesis is discussed. The motivation is to deactivate the memory refresh circuitry, apply power down or disable the clock signals during the inactive periods of operation of circuit elements, and thus minimize the power consumption. Since it is impractical to have a separate set of control signals for each circuit element (otherwise, the control itself would consume a lot of power), it is advisable to partition a circuit based on the activity patterns of its elements so that the partitions can be switched into sleep mode for long periods of time. In this paper, we formulate this partitioning problem and show that it is NP-hard. We present Geo Part , a g e ometric partitioning heuristic for this problem. An ecient implementation of Geo Part using segment tree data structure is discussed. Experimental results are encouraging.

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Simultaneous Driver And Wire Sizing For Performance And Power Optimization*

Cited by 46 publications

References 0 publications

Interconnect design for deep submicron ICs

Interconnect design for deep submicron ICs

Digital Circuit Optimization via Geometric Programming

System partitioning to maximize sleep time

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