Simulation of non-classical faults on the gate level-fault modeling

Alt, J.; Mahlstedt, U.

doi:10.1109/vtest.1993.313377

“…The algorithm uses the behaviour of CMOS transistors in digital circuits [48] and describes the circuit in an arithmetic equation. An equation is defined and describes circuit behaviour in detail according to all possible input combinations.…”

Section: Arithmetic Equation Of the Circuitmentioning

confidence: 99%

Fault Detection for ASIC Design Reliability on Resistive Delay Faults and Strength-Based Soft-Errors

Javaheri¹

2023

Preprint

0

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Soft-errors (SEs) and delay faults (DFs) frequently occur in modern high-density, high-speed, low-power VLSI circuits. Therefore, SE hardened design and DF testing are essential. This thesis introduces two novel methods for soft-error detection and delay fault propagation in nanometre technology. A new idea is proposed to propagate those delay faults that are not causing logic failure at the site of the defect, but the delay makes the circuit more prone to soft-errors that manifest the effect of delay faults. This approach propagates the fault from the fault location by mapping a nine-valued voltage model on top of a five-valued voltage model to convert delay faults to static faults. This original idea reduces the complexity of delay fault propagation. This thesis introduces an original approach toward soft-error detection based on the strength violation in the circuit. This research shows that transient pulses of less than threshold voltage will cause soft-errors without altering the logic value at the strike location. This method will increase the Soft-Error Rates (SER) for all existing methods if strength-based Soft-Error detection will be considered. The offered approach uses a novel coding system that carries both logic and strength which applies to certain logic functions that are sensitive to strength variations. A wide range of soft-errors are the result of strength violation in switch-level that have never been investigated before.

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“…The algorithm uses the behaviour of CMOS transistors in digital circuits [48] and describes the circuit in an arithmetic equation. An equation is defined and describes circuit behaviour in detail according to all possible input combinations.…”

Section: Arithmetic Equation Of the Circuitmentioning

confidence: 99%

Fault Detection for ASIC Design Reliability on Resistive Delay Faults and Strength-Based Soft-Errors

Javaheri¹

2023

Preprint

0

View full text Add to dashboard Cite

Soft-errors (SEs) and delay faults (DFs) frequently occur in modern high-density, high-speed, low-power VLSI circuits. Therefore, SE hardened design and DF testing are essential. This thesis introduces two novel methods for soft-error detection and delay fault propagation in nanometre technology. A new idea is proposed to propagate those delay faults that are not causing logic failure at the site of the defect, but the delay makes the circuit more prone to soft-errors that manifest the effect of delay faults. This approach propagates the fault from the fault location by mapping a nine-valued voltage model on top of a five-valued voltage model to convert delay faults to static faults. This original idea reduces the complexity of delay fault propagation. This thesis introduces an original approach toward soft-error detection based on the strength violation in the circuit. This research shows that transient pulses of less than threshold voltage will cause soft-errors without altering the logic value at the strike location. This method will increase the Soft-Error Rates (SER) for all existing methods if strength-based Soft-Error detection will be considered. The offered approach uses a novel coding system that carries both logic and strength which applies to certain logic functions that are sensitive to strength variations. A wide range of soft-errors are the result of strength violation in switch-level that have never been investigated before.

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“…Other fault models at the gate level include function conversion, bridging faults, transition faults, etc. [16] CMOS scaling is predicted to reach a brick wall by the next decade. Single-electron tunneling (SET) [17], quantum-dot cellular automata (QCA) [18] and molecular electronics [20] have been extensively investigated as possible alternative technologies for the electronics beyond CMOS.…”

Section: Failures and Faults In Nanoelectronicsmentioning

confidence: 99%

Faults, Error Bounds and Reliability of Nanoelectronic Circuits

Han

¹

,

Taylor

²

,

Gao

³

et al.

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)

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This paper is concerned with faults, error bounds and reliability modeling of nanotechnology-based circuits. First, we briefly review failure mechanisms and fault models in nanoelectronics. Second, reliability functions based on probabilistic models are developed for unreliable logic gates. We then show that fundamental gate error bounds for general probabilistic computation can be derived using the nonlinear mapping functions constructed from the gate models. Finally, an analytical approach is proposed for estimating reliabilities of nanoelectronic circuits. This approach is based on the probabilistic modeling of unreliable logic gates and interconnects. In spite of the approximations used in probabilistic modeling, our study suggests that the proposed approach provides a simple and efficient way to model the reliability of nanoelectronic circuits.

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Simulation of non-classical faults on the gate level-fault modeling

Cited by 15 publications

References 7 publications

Fault Detection for ASIC Design Reliability on Resistive Delay Faults and Strength-Based Soft-Errors

Fault Detection for ASIC Design Reliability on Resistive Delay Faults and Strength-Based Soft-Errors

Fault Detection for ASIC Design Reliability on Resistive Delay Faults and Strength-Based Soft-Errors

Faults, Error Bounds and Reliability of Nanoelectronic Circuits

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