IEEE Custom Integrated Circuits Conference 2010 2010
DOI: 10.1109/cicc.2010.5617422
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Simulation methodology and flow integration for 3D IC stress management

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Cited by 13 publications
(4 citation statements)
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“…While both the silicon and packaging world have mechanical stress modeling practices they have traditionally not been cognizant of one another established interfaces do not exist. While mechanical stress is an issue for both 2D and 3D product, much of the development of this flow has been started in the 3D world [5][6][7][8] due to its more complex nature but is of course applicable to 2D product. Additionally for a modeling flow to be useful it needs proper characterization of materials and processes to feed the models and of course builds of test cases to anchor and validate the models.…”
Section: Discussionmentioning
confidence: 99%
“…While both the silicon and packaging world have mechanical stress modeling practices they have traditionally not been cognizant of one another established interfaces do not exist. While mechanical stress is an issue for both 2D and 3D product, much of the development of this flow has been started in the 3D world [5][6][7][8] due to its more complex nature but is of course applicable to 2D product. Additionally for a modeling flow to be useful it needs proper characterization of materials and processes to feed the models and of course builds of test cases to anchor and validate the models.…”
Section: Discussionmentioning
confidence: 99%
“…However, we do not use a specific threshold value for the von Mises criterion in this work, since it is greatly affected by fabrication process. Figure 4 shows our simulation structure, where the dimensions of our baseline simulation structures are based on the fabricated and/or published data [2,8]. In this work, we specifically examine the stress distribution on device layer for each die shown in red lines in Figure 4.…”
Section: D Ic/package Stress Modelingmentioning
confidence: 99%
“…As for the package domain, many works focused on the reliability of package bump (= C4 bump) [9]. Recently, authors in [8] showed the significant impact of package components on the chip domain stress. They proposed a stress exchange file to transfer the boundary conditions from package-level to silicon-level analysis.…”
Section: Introductionmentioning
confidence: 99%
“…observed that the c-axis of the b-Sn grains in a Sn3.5Ag solder joint rotated toward a direction parallel to the interface between the solder joint and the under-bump metallization (UBM) due to thermo-mechanical stress [13]. Abdelhadi et al reported faster growth of the Cu 3 Sn IMC in smaller Sn3.5Ag solder joints and attributed this result to the effect of stress on the diffusion rates of Sn and Cu. [15].…”
Section: Introductionmentioning
confidence: 97%