2022
DOI: 10.3389/fnins.2021.728460
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Simulating the Cortical Microcircuit Significantly Faster Than Real Time on the IBM INC-3000 Neural Supercomputer

Abstract: This article employs the new IBM INC-3000 prototype FPGA-based neural supercomputer to implement a widely used model of the cortical microcircuit. With approximately 80,000 neurons and 300 Million synapses this model has become a benchmark network for comparing simulation architectures with regard to performance. To the best of our knowledge, the achieved speed-up factor is 2.4 times larger than the highest speed-up factor reported in the literature and four times larger than biological real time demonstrating… Show more

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Cited by 12 publications
(24 citation statements)
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References 43 publications
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“…To our best knowledge, we report the lowest RTF so far at a competitive energy consumption (table 2). There are, however, data [22] on an even smaller RTF for a dedicated FPGA supercomputer using on-the-fly generation of connectivity. Our results expose that cache sensitive binding of threads increases performance.…”
Section: Discussionmentioning
confidence: 99%
“…To our best knowledge, we report the lowest RTF so far at a competitive energy consumption (table 2). There are, however, data [22] on an even smaller RTF for a dedicated FPGA supercomputer using on-the-fly generation of connectivity. Our results expose that cache sensitive binding of threads increases performance.…”
Section: Discussionmentioning
confidence: 99%
“…The first is a functional requirement: even though the current development does not yet include plasticity, in order to be able to cope with synaptic and structural plasticity algorithms in future, the synaptic connections must be stored, accessible, and changeable. In contrast, for static networks, performance-efficient solutions have been developed which makes use of a procedural connectivity generation approach (Knight and Nowotny, 2021 ; Heittmann et al, 2022 ) where the synaptic connections are determined algorithmically during the simulation, thus avoiding having to retrieve them from memory. The second is a resource constraint due to technical limitations of the technology: fast, low-latency, on-chip block RAM (BRAM) would be ideal to hold this data, but BRAM is a limited FPGA resource and the memory requirement for storing a network's connectivity data is demanding.…”
Section: Overview Of the Hybrid Neuromorphic Compute (Hnc) Nodementioning
confidence: 99%
“…The system is highly flexible and applications can off-load algorithms and accelerate them using the programmable logic of the Zynq SoC devices. An example of such an application is the implementation of the cortical microcircuit model (Potjans and Diesmann, 2014 ) on the INC-3000 presented in Heittmann et al ( 2022 )—a reproduction of an equivalent NEST implementation and on the SpiNNaker neuromorphic system (cf. van Albada et al, 2018 ).…”
Section: Introductionmentioning
confidence: 99%
“…The system enables energy-efficient neuronal network simulations, offering highly accelerated operations. Another promising project in this field is SpiNNaker (Furber et al, 2014 ), which recently achieved biological real-time simulations of a cortical microcircuit model (Rhodes et al, 2020 ) proposed by Potjans and Diesmann ( 2014 ) (which has since been simulated sub-realtime with NEST (Kurth et al, 2022 ) and with an FPGA-based neural supercomputer (Heittmann et al, 2022 ). This result was made possible by its architecture designed for efficient spike communication, performed with an optimized transmission system of small data packets.…”
Section: Introductionmentioning
confidence: 99%