Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnects

Abstract

ABSTRACT500+ MHz designs using deep-submicron (DSM) copper interconnects require accurate and efficient modeling of cladding-metals' frequency-dependent impedance [1]. In this paper, for the first time, we simulate and describe the current distribution inside a copper-based interconnect in a rich set of multi-line structures. The difference of the resistivities of copper alloy and the cladding metals causes a non-monotonic current density versus cross-wire axis relation. The same situation does not occur for the state-of-the-art aluminum processes. It enlarges the inductance by more than 12 percent. Simulating the frequency dependence of the inductance with this property, we find that PEEC [2][3] can simulate cladded wire profile to achieve accurate inductance extraction. Other approximate methods result in inaccurate and lower inductance values. A new modeling methodology based on library look-up is then proposed to make an efficient field-solver based extraction flow for realistic DSM designs. KEYWORDSCopper interconnect, skin-effect current distribution, cladding material, electromagnetic field solvers.

Expression of Concern: Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk

“…Note that same kind of results can be produced for copper interconnects. Finer discretization may be needed for cladded copper lines [6].…”

A physics-based VLSI interconnect model including substrate and conductor skin effects

“…With respect to the substrate conductivity and signal frequency, in general three wave propagation modes can be distinguished which lead to different formulae for the line parameters (quasi-TEM, slowwave and skin-effect mode, respectively) [9]. Recently in our work [4] and in [2,5] the authors succeeded in describing the frequency-dependent transmission line parameters of onchip interconnects on lossy silicon substrate in a unified way. Therefore, simple and fast methods and formulae will be necessary to generate electrical models for the on-chip interconnects that accurately account for such effects as delay, crosstalk and resistive voltage drops.…”

“…In this case losses in the semiconductor substrate become significant and should be taken into account. In order to accomplish this, it is necessary to analyse and model the broadband characteristics [2,[4][5][6][7][8][9] of the on-chip interconnects on a silicon oxide-silicon substrate. With respect to the substrate conductivity and signal frequency, in general three wave propagation modes can be distinguished which lead to different formulae for the line parameters (quasi-TEM, slowwave and skin-effect mode, respectively) [9].…”