Simulated Fault Injection Using Simulator Modification Technique

Na, Jongwhoa; Lee, Dongwoo

doi:10.4218/etrij.11.0110.0106

Cited by 9 publications

(7 citation statements)

References 11 publications

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“…VITAL defines two levels of support. VITAL level 0 requires the definition of a level 0 attribute (line 21 of Listing 1), using ports of type std ulogic and std logic vector with no underscores in the port names (lines [18][19], and special naming convention for timing generics (lines 8-11, with ports names prefixed as tpid -interconnect path delay that represents the delay between components-and tpd -propagation delay that represents the pin-to-pin delay within a component). Compliance with VITAL level 0 provides SDF back annotation and negative timing constraints.…”

Section: The Vital Standardmentioning

confidence: 99%

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Simulating the effects of logic faults in implementation-level VITAL-compliant models

2018

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Simulation-based fault injection (SBFI) is a well-known technique to assess the dependability of hardware designs specified using Hardware Description Languages (HDL). Although logic faults are usually introduced in models defined at the Register Transfer Level (RTL), most accurate results can be obtained by considering implementation-level ones, which reflect the actual structure and timing of the circuit. These models consist of a list of interconnected technology-specific components (macrocells), provided by vendors and annotated with post-place-and-route delays. Macrocells described in the Very High Speed Integrated Circuit HDL (VHDL) should also comply with the VHDL Initiative Towards Application Specific Integrated Circuit Libraries (VITAL) standard to be interoperable across standard simulators. However, the rigid architecture imposed by VITAL makes that fault injection procedures applied at RTL cannot be used straightforwardly. This work identifies a set of generic operations on VITAL-compliant macrocells that are later used to define how to accurately simulate the effects of common logic fault models. The

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Section: The Vital Standardmentioning

confidence: 99%

“…Alternative SBFI approaches proposed the development of non-standard simulators to speed-up the simulation of faults, like the one targeting IcarusVerilog models [19] or those using GPGPUs [15]. However, these approaches are not generic and cannot be applied to off-the-shelf EDA tools.…”

Section: Introductionmentioning

confidence: 99%

Simulating the effects of logic faults in implementation-level VITAL-compliant models

2018

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“…The second group investigated tool acceleration to reduce the simulation time, wherein the tool identifies and removes unnecessary or redundant operations of the SFI , . One such approach is to use an efficient SFI management strategy, which uses a CF mechanism.…”

Section: Overview Of the Acceleration Of The Fault Injection Techniquesmentioning

confidence: 99%

“…From our experience with SFI, when we performed fault‐injection campaigns with a large number of faults and various injection locations, times, and complex co‐simulation targets, we found that some parts of the SFI process were redundant , . If we can remove the redundant process in the SFI campaign, we may be able to accelerate the test time of the SFI.…”

Section: Introductionmentioning

confidence: 99%

Acceleration of Simulated Fault Injection Using a Checkpoint Forwarding Technique

Na¹,

Lee²

2017

ETRI Journal

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Simulated fault injection (SFI) is widely used to assess the effectiveness of fault tolerance mechanisms in safety-critical embedded systems (SCESs) because of its advantages such as controllability and observability. However, the long test time of SFI due to the large number of test cases and the complex simulation models of modern SCESs has been identified as a limiting factor. We present a method that can accelerate an SFI tool using a checkpoint forwarding (CF) technique. To evaluate the performance of CF-based SFI (CF-SFI), we have developed a CF mechanism using Verilog faultinjection tools and two systems under test (SUT): a single-core-based co-simulation model and a triple modular redundant co-simulation model. Both systems use the Verilog simulation model of the OpenRISC 1200 processor and can execute the embedded benchmarks from MiBench. We investigate the effectiveness of the CF mechanism and evaluate the two SUTs by measuring the test time as well as the failure rates. Compared to the SFI with no CF mechanism, the proposed CF-SFI approach reduces the test time of the two SUTs by 29%-45%.

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“…Three basic categories of fault injection include hardware implemented fault injection, software implemented fault injection and simulated fault injection. Advantages of simulated fault injection include cost reduction in the design process due to early diagnosis, avoidance of redesign in case of error and thus short time-to-market [13], [14]. Very high speed integrated circuits Hardware Description Language [VHDL] based fault injection receives wide spread recognition due to its flexibility combined with a high degree of controllability and observability on all the components of the simulated model [12].…”

Section: Introductionmentioning

confidence: 99%

Black Box Model based Self Healing Solution for Stuck at Faults in Digital Circuits

Meyyappan¹,

Alamelumangai²

2017

IJECE

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The paper proposes a design strategy to retain the true nature of the output in the event of occurrence of stuck at faults at the interconnect levels of digital circuits. The procedure endeavours to design a combinational architecture which includes attributes to identify stuck at faults present in the intermediate lines and involves a healing mechanism to redress the same. The simulated fault injection procedure introduces both single as well as multiple stuck-at faults at the interconnect levels of a two level combinational circuit in accordance with the directives of a control signal. The inherent heal facility attached to the formulation enables to reach out the fault free output even in the presence of faults. The Modelsim based simulation results obtained for the Circuit Under Test [CUT] implemented using a Read Only Memory [ROM], proclaim the ability of the system to survive itself from the influence of faults. The comparison made with the traditional Triple Modular Redundancy [TMR] exhibits the superiority of the scheme in terms of fault coverage and area overhead.

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Simulated Fault Injection Using Simulator Modification Technique

Cited by 9 publications

References 11 publications

Simulating the effects of logic faults in implementation-level VITAL-compliant models

Simulating the effects of logic faults in implementation-level VITAL-compliant models

Acceleration of Simulated Fault Injection Using a Checkpoint Forwarding Technique

Black Box Model based Self Healing Solution for Stuck at Faults in Digital Circuits

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