Simulated annealing-based placement for microfluidic large scale integration (mLSI) chips

Abstract

Abstract-Microfluidic large-scale integration (mLSI) chips comprise hundreds or thousands of microvalves integrated into a chemically inert elastomeric substrate. The design of these chips is time-consuming, error-prone, and presently performed by hand. To enhance design automation, a routability-oriented placement algorithm based on simulated annealing is introduced. This paper investigates relevant issues including: (1) grid representation; (2) perturbation operations; (3) objective function; (4) uniform vs. heterogeneous component sizes; (5) spacing rules and their effect on routability; and (6) random vs. directed initial placement. Our results show how the above issues affect both the pre-routing estimate on the routability of the chips, the number of flow channel intersections (each of which requires the insertion of several microvalves), and total channel distance as reported by our router.

Flow-Layer Physical Design for Microchips Based on Monolithic Membrane Valves

“…Having one layer for fluid flow imposes the constraint that only planar LoC architectures can be realized in this technology. It is possible to planarize a nonplanar architecture by inserting microvalves to act as switches at fluid channel intersection points [8]; however, doing so is problematic because additional external control lines are required to actuate the switches. The number of external control lines is typically limited as a design rule, and adding more control lines tends to reduce reliability after fabrication.…”

“…Prior work on flow layer component placement uses simulated annealing [8], [9], which is based on randomization and iterative improvement. Simulated annealing does not guarantee a planar layout, even if the netlist being placed is planar.…”

Diagonal Component Expansion for Flow-Layer Placement of Flow-Based Microfluidic Biochips

“…• Simulated Annealing (SA) refers to the simulated annealing algorithm proposed by Mc-Daniel et al [11], which uses Hadlock's Algorithm for channel routing. SA cannot guarantee a planar layout for planar netlists; all other methods included here provide this guarantee.…”

“…We used the same SA parameter settings as in Ref. [11], which coincidentally had SA running approximately as fast as the planar embedding methods that we evaluated here. It is also worth noting that SA uses a router based on Hadlock's Algorithm, as opposed to the network flow-based router used by the planar embedding heuristics [22].…”

“…Non-planar mVLSI netlist synthesis may consider multiple objectives including minimizing the number of flow channel crossing, minimizing area, and minimizing flow channel length. Researchers have proposed placers using simulated annealing [11,14,21] and iterated cluster expansion (ICE) [17]. Non-planar routing algorithms may reduce fluid routing channel length, but do not limit the number of channel crossings [8].…”