Flow-Layer Physical Design for Microchips Based on Monolithic Membrane Valves

ACM Trans. Embed. Comput. Syst.

2017

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Continuous flow-based microfluidic devices have seen a huge increase in interest because of their ability to automate and miniaturize biochemistry and biological processes, as well as their promise of creating a programmable platform for chemical and biological experimentation. The major hurdle in the adoption of these types of devices is in the design, which is largely done by hand using tools such as AutoCAD or SolidWorks, which require immense domain knowledge and are hard to scale. This paper investigates the problem of automated physical design for continuous flow-based microfluidic very large scale integration (mVLSI) biochips, starting from a netlist specification of the flow layer. After an initial planar graph embedding, vertices in the netlist are expanded into two-dimensional components, followed by fluid channel routing. A new heuristic, DIagonal Component Expansion (DICE) is introduced for the component expansion step. Compared to a baseline expansion method, DICE improves area utilization by a factor of 8.90x and reduces average fluid routing channel length by 47.4%.

Section: Planar Mvlsi Netlist Embeddingsupporting

confidence: 80%

Section: Shift Expansionmentioning

confidence: 99%

Diagonal Component Expansion for Flow-Layer Placement of Flow-Based Microfluidic Biochips

ACM Trans. Embed. Comput. Syst.

2017

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“…Quantitatively, Directed Placement yields shorter channel route lengths than several existing placement heuristics when used in conjunction with existing routing methods. Specifically, we compare against three previous microfluidic placement methods: Simulated Annealing [29], which was adapted from semiconductor VLSI placement; Planar Placement [30], which adapts planar graph layout methods for microfluidics; and Diagonal Component Expansion [6], which is a more refined variant of the Planar Placement method. Directed Placement is shown to be far more effective than three prior heuristics in terms of improving area utilization and reducing average channel length.…”

Section: Introductionmentioning

confidence: 99%

Directed Placement for mVLSI Devices

J. Emerg. Technol. Comput. Syst.

2019

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Continuous-flow microfluidic devices based on integrated channel networks are becoming increasingly prevalent in research in the biological sciences. At present, these devices are physically laid out by hand by domain experts who understand both the underlying technology and the biological functions that will execute on fabricated devices. The lack of a design science that is specific to microfluidic technology creates a substantial barrier to entry. To address this concern, this article introduces Directed Placement, a physical design algorithm that leverages the natural "directedness" in most modern microfluidic designs: fluid enters at designated inputs, flows through a linear or tree-based network of channels and fluidic components, and exits the device at dedicated outputs. Directed placement creates physical layouts that share many principle similarities to those created by domain experts. Directed placement allows components to be placed closer to their neighbors compared to existing layout algorithms based on planar graph embedding or simulated annealing, leading to an average reduction in laid-out fluid channel length of 91% while improving area utilization by 8% on average. Directed placement is compatible with both passive and active microfluidic devices and is compatible with a variety of mainstream manufacturing technologies.

“…is unlikely that this approach will scale to large devices. Meanwhile, tractable heuristics based on planar graph embedding [5] yield solutions that are far from optimal. This paper adapts seam carving [2], an image size reduction technique, to improve the area utilization of lowquality mVLSI layouts.…”

Section: Introductionmentioning

confidence: 99%

Reducing Microfluidic Very Large Scale Integration (mVLSI) Chip Area by Seam Carving

Proceedings of the Great Lakes Symposium on VLSI 2017

2017

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This paper introduces a technique based on seam carving to reduce the area of microfluidic very large scale integration (mVLSI) chips. Seam carving repeatedly identifies small slices of the device that can be safely removed (carved) and patched without adversely affecting device functionality. Using non-linear seam carving we achieve an average improvement of 4.28x in area utilization and an average reduction in fluid routing channel length of 53%.