Simplified Trellis Min–Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes

Lacruz, Jesus O.; García-Herrero, Francisco; Declercq, David; Valls, Javier

doi:10.1109/tvlsi.2014.2344113

Cited by 39 publications

(138 citation statements)

References 18 publications

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“…If we compare this work to the most efficient architectures found in literature [34] and [42], we can see that the maximum frequency is increased in 50% and 26% respectively due to the reduction of the routing congestion. On the other hand, area is about 43% larger than the decoder from [34] and 3 times smaller than the one in [42].…”

Section: I)mentioning

confidence: 80%

“…This research takes as starting point the T-MM algorithm and decoder architecture from the previous chapter and the T-EMS approach in its simplified version using the results from [42]. The research was focused in the reduction of complexity in the CN processor by means of a novel approach to avoid the use of two-minimum finders to compute the 53 two most reliable messages.…”

Section: Discussionmentioning

confidence: 99%

“…To a better understanding of the messagepassing between check node and variable node, a short explanation of the basics operations performed in the check node is included next, for more details about the different decoding processes we refer to [16] and [42].…”

Section: Non-binary Ldpc Message Passingmentioning

confidence: 99%

“…This implementation did not sacrifice efficiency in terms of throughput/area compared to other serial implementations based on trellis [34] and increased throughput more than three times. Further improvements were introduced with the Trellis Min-max (TMM) in [42]. Despite this, the decoder from [42] required 14.7mm 2 of area with a 90nm CMOS process and reached a throughput of 660Mbps, which is far from the results of modern binary LDPC decoders for the same technology (9.6mm 2 , 45.42Gbps) [47].…”

Section: Introductionmentioning

confidence: 99%

“…This has a great impact in both area and throughput specially for high rate codes. As an example, an implementation for the same code as in [42] and [34] achieves 981Mbps of throughput with an area of 10.6mm…”

Section: Introductionmentioning

confidence: 99%

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VLSI algorithms and architectures for non-binary-LDPC decoding

Lacruz¹,

Jesús²

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This thesis studies the design of low-complexity soft-decision Non-Binary LowDensity Parity-Check (NB-LDPC) decoding algorithms and their corresponding hardware architectures suitable for decoding high-rate codes at high throughput (hundreds of Mbps and Gbps).In the first part of the thesis the main aspects concerning to the NB-LDPC codes are analyzed, including a study of the main bottlenecks of conventional softdecision decoding algorithms (Q-ary Sum of Products (QSPA), Extended MinSum (EMS), Min-Max and Trellis-Extended Min-Sum (T-EMS)) and their corresponding hardware architectures. Despite the limitations of T-EMS algorithm (high complexity in the Check Node (CN) processor, wiring congestion due to the high number of exchanged messages between processors and the inability to implement decoders over high-order Galois fields due to the high decoder complexity), it was selected as starting point for this thesis due to its capability to reach high-throughput.Taking into account the identified limitations of the T-EMS algorithm, the second part of the thesis includes six papers with the results of the research made in order to mitigate the T-EMS disadvantages, offering solutions that reduce the area, the latency and increase the throughput compared to previous proposals from literature without sacrificing coding gain. Specifically, five low-complexity decoding algorithms are proposed, which introduce simplifications in different parts of the decoding process. Besides, five complete decoder architectures are designed and implemented on a 90nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The results show an achievement in throughput higher than 1Gbps and an area less than 10 mm 2 . The increase in throughput is 120% and the reduction in area is 53% compared to previous implementations of T-EMS, for the (837,726) NB-LDPC code over GF(32). The proposed decoders reduce the CN area, latency, wiring between CN and Variable Node (VN) processor and the number of storage elements required in the decoder. Considering that these proposals improve both area and speed, the efficiency parameter (Mbps / Million iii NAND gates) is increased in almost five times compared to other proposals from literature.The improvements in terms of area allow us to implement NB-LDPC decoders over high-order fields which had not been possible until now due to the highcomplexity of decoders previously proposed in literature. Therefore, we present the first post-place and route report for high-rate codes over high-order fields higher than Galois Field (GF)(32). For example, for the (1536,1344) NB-LDPC code over GF (64) ResumenEn esta tesis se aborda el estudio del diseño de algoritmos de baja complejidad para la decodificación de códigos de comprobación de paridad de baja densidad no binarios (NB-LDPC) y sus correspondientes arquitecturas apropiadas para decodificar códigos de alta tasa a altas velocidades (cientos de Mbps y Gbps).En la primera parte de la tesis los principales aspectos concernientes a los códi-gos NB-LDPC s...

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