Simplified selective fault tolerance technique for protection of selected inputs via triple modular redundancy systems

Agnola, Liviu; Vlăduţiu, Mircea; Udrescu, Mihai; Prodan, Lucian

doi:10.1109/saci.2012.6250014

Cited by 2 publications

(4 citation statements)

References 12 publications

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“…Furthermore, with N = 256, which covers 50% of the input patterns, the error coverage improvement results in 5.27%. The resulting area cost of the PSFT technique for circuit Z9sym with N = 128 and N = 256 is 99% (TMR impr = 101%) and 139% (TMR impr = 61%), respectively, which is similar to the area cost reported in [2,4]. The area cost of the two techniques is similar in all cases.…”

Section: Simulation Resultssupporting

confidence: 69%

“…The selective fault tolerance techniques presented in [2] and [4] rely on an arbitrary selection of its workload to protect without examining the susceptibility to either faults or Table 6 Permanent (induced by single stuck-at and transition) and Transient (induced by erroneous output transitions and by bit-flips) EC, area cost and the improvement over TMR of the proposed technique with C p = 0.1 Tables 4, 5 and 6 show that the proposed PSFT technique (S pp ) offers various error coverage improvements for both timing-independent and timing-dependent errors compared to an unranked selection of patterns (S rp ). Applying PSFT to circuit Z9sym, Table 4 shows that the S pp set consistently exhibits higher error coverage than the S rp set.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…A simplified method for SFT was proposed in [2], where the circuits s 2 and s 3 are replaced by identical circuits. These circuits are the minimal combinational circuits that for an input pattern within the protected set X 1 , exhibit the same output as the original circuit S 1 .…”

Section: Selective Fault Tolerancementioning

confidence: 99%

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Susceptible Workload Evaluation and Protection using Selective Fault Tolerance

et al. 2017

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Low power fault tolerance design techniques trade reliability to reduce the area cost and the power overhead of integrated circuits by protecting only a subset of their workload or their most vulnerable parts. However, in the presence of faults not all workloads are equally susceptible to errors. In this paper, we present a low power fault tolerance design technique that selects and protects the most susceptible workload. We propose to rank the workload susceptibility as the likelihood of any error to bypass the logic masking of the circuit and propagate to its outputs. The susceptible workload is protected by a partial Triple Modular Redundancy (TMR) scheme. We evaluate the proposed technique on timing-independent and timing-dependent errors induced by permanent and transient faults. In comparison with unranked selective fault tolerance approach, we demonstrate a) a similar error coverage with a 39.7% average reduction of the area overhead or b) a 86.9% average error coverage improvement for a similar area overhead. For the same area overhead case, we observe an error coverage improvement of 53.1% and 53.5% against permanent stuck-at and transition faults, respectively, and an average error coverage improvement of 151.8% and 89.0% against timing-dependent and timing-independent transient faults, respectively. Compared to TMR, the proposed technique achieves an area and power overhead reduction of 145.8% to 182.0%.

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Section: Simulation Resultssupporting

confidence: 69%

Section: Simulation Resultsmentioning

confidence: 99%

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Susceptible Workload Evaluation and Protection using Selective Fault Tolerance

et al. 2017

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“…A simplified method for SFT was proposed in [20], where the circuits s 2 and s 3 are replaced by identical circuits. These circuits are the minimal combinational circuits that for an input pattern within the protected set X 1 , exhibit the same output as the original circuit S 1 .…”

Section: A Selective Fault Tolerancementioning

confidence: 99%

Susceptible workload driven selective fault tolerance using a probabilistic fault model

Gutierrez

Tenentes

Kázmierski

2016

2016 IEEE 22nd International Symposium on on-Line Testing and Robust System Design (IOLTS)

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Abstract-In this paper, we present a novel fault tolerance design technique, which is applicable at the register transfer level, based on protecting the functionality of logic circuits using a probabilistic fault model. The proposed technique selects the most susceptible workload of combinational circuits to protect against probabilistic faults. The workload susceptibility is ranked as the likelihood of any fault to bypass the inherent logical masking of the circuit and propagate an erroneous response to its outputs, when that workload is executed. The workload protection is achieved through a Triple Modular Redundancy (TMR) scheme by using the patterns that have been evaluated as most susceptible. We apply the proposed technique on LGSynth91 and ISCAS85 benchmarks and evaluate its fault tolerance capabilities against errors induced by permanent faults and soft errors. We show that the proposed technique, when it is applied to protect only the 32 most susceptible patterns, achieves on average of all the examined benchmarks, an error coverage improvement of 98% and 94% against errors induced by single stuck-at faults (permanent faults) and soft errors (transient faults), respectively, compared to a reduced TMR scheme that protects the same number of susceptible patterns without ranking them.

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Simplified selective fault tolerance technique for protection of selected inputs via triple modular redundancy systems

Cited by 2 publications

References 12 publications

Susceptible Workload Evaluation and Protection using Selective Fault Tolerance

Susceptible Workload Evaluation and Protection using Selective Fault Tolerance

Susceptible workload driven selective fault tolerance using a probabilistic fault model

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