Susceptible workload driven selective fault tolerance using a probabilistic fault model

Abstract

Abstract-In this paper, we present a novel fault tolerance design technique, which is applicable at the register transfer level, based on protecting the functionality of logic circuits using a probabilistic fault model. The proposed technique selects the most susceptible workload of combinational circuits to protect against probabilistic faults. The workload susceptibility is ranked as the likelihood of any fault to bypass the inherent logical masking of the circuit and propagate an erroneous response to its outputs, when that workload is executed. The workload protection is achieved through a Triple Modular Redundancy (TMR) scheme by using the patterns that have been evaluated as most susceptible. We apply the proposed technique on LGSynth91 and ISCAS85 benchmarks and evaluate its fault tolerance capabilities against errors induced by permanent faults and soft errors. We show that the proposed technique, when it is applied to protect only the 32 most susceptible patterns, achieves on average of all the examined benchmarks, an error coverage improvement of 98% and 94% against errors induced by single stuck-at faults (permanent faults) and soft errors (transient faults), respectively, compared to a reduced TMR scheme that protects the same number of susceptible patterns without ranking them.

Low cost error monitoring for improved maintainability of IoT applications

“…Figure 3b presents the proposed design flow of the SEB ranking module and for the insertion of the SPMs on the chip. The process of workload profiling is performed depending on whether the workload is biased or unbiased [10], [11]. For a biased workload, the correlation and variations of the input patterns are known, which makes the mean signal probability M sp and the signature window bounds W min and W max For an unbiased workload, where its input patterns are uncorrelated and considered to be equally likely to occur, an error-free simulation of a large number of unbiased workloads is required to compute the M sp .…”

“…The next column shows the error detection latency (EDL), which is given by the workload size S required for the online signal probabilities to converge. Following is the number of monitored cones C = [1,5,10,15]. The next columns present the EC of errors induced by 1, 2, or 3 input bit-flips in the selected cones, which are calculated as shown in (3).…”

Low power probabilistic online monitoring of systematic erroneous behaviour

“…An unbiased workload of size S = 5000 was used and the signature window was defined as w=[M sp ± 3σ], with σ = 0.00534. The fault coverage (FC) of 52.55% is calculated by counting all the SSA faults that cause the OSP to fall outside the w. Not all faults present during normal operation bypass the inherent logic masking of a circuit [3]. When fault is masked, few errors are propagated with a small effect in the OSPs.…”

Susceptible Workload Evaluation and Protection using Selective Fault Tolerance

“…Preliminary results of this technique were presented in [10], where only the timing-independent errors induced by stuck-at faults and input bit-flips were considered. The workload susceptibility is ranked as the likelihood of any error to bypass the inherent logic masking of the circuit and propagate an erroneous response to its outputs when that workload is executed.…”