Simplified merged processing element for successive‐cancellation polar decoder

Abstract

Novel simplified merged processing element (SMPE) architectures to design a low-complexity successive-cancellation (SC) polar decoder are presented. The proposed SMPE architectures reduce the number of sign-magnitude conversions and switch networks, relative to those of the conventional merged processing element. Synthesis results show that the (1024, 512) SC polar decoder using the proposed SMPE architectures significantly decreases hardware complexity and improves technology scaled normalised throughput, as compared to those of the previously reported architectures.

Successive cancellation decoding of polar codes using new hybrid processing element

“…Every stage is composed of the kernels f and g appropriately scheduled to decode the data. The f and g kernels function based on ( 6) and (7). where ûsum decides between addition and subtraction in the kernel g, c and d represent the LLR inputs.…”

“…On careful examination of the merged processing element in [2], it was noted that during the g node operation, both addition and subtraction are performed in all the iterations. But for the successful functioning of the decoder, only one operation is sufficient and it is decided by the partial sum of the previously decoded bits as (7). The proposed NHPE uses a unique scheme of combinational logic to eliminate the subtraction operation throughout the entire architecture along with a 2x1 multiplexer that chooses between addition and subtraction.…”

“…A novel merged processing element for SCD based on one's complement was proposed in [6] which helped to increase the throughput. In [7], a Novel simplified merged processing element (SMPE) architecture was proposed for SCD, and the decoding tree was constructed with low complexity. The SCD has the greatest throughput and energy per bit [8] compared to other decoders.…”