Simplified low-temperature wafer-level hybrid bonding using pillar bump and photosensitive adhesive for three-dimensional integrated circuit integration

Yao, Mingjun; Fan, Jun; Zhao, Ning; Xiao, Zhiyi; Ma, Haitao

doi:10.1007/s10854-017-6642-y

Cited by 7 publications

(2 citation statements)

References 14 publications

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“…It is necessary to develop bonding adhesives before using BCB or polyimide for hybrid bonding. One can use dry etching, photopolymer adhesives [219], or spin coating and polishing [220]. An alternative method for creating adhesive layers involves applying dry films or laminating insulator underfill onto wafers before bonding [221,222].…”

Section: Hybrid Bondingmentioning

confidence: 99%

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

Jang,

Sharma,

Jung

2023

Materials

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Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency.

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Section: Hybrid Bondingmentioning

confidence: 99%

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

Jang,

Sharma,

Jung

2023

Materials

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“…As shown in Figure 21, for Cu/polymer hybrid bonding, to avoid CMP or fly-cut processes, some researchers use an asymmetrical hybrid bonding structure [61][62][63]. In contrast, a symmetrical hybrid bonding structure typically requires the CMP or fly-cut process to ensure that the double-sided Cu/polymer structure has sufficient flatness and is on the same plane to achieve a good hybrid bonding interface [64].…”

Section: Cu/polymer Hybrid Bondingmentioning

confidence: 99%

Cu-Based Thermocompression Bonding and Cu/Dielectric Hybrid Bonding for Three-Dimensional Integrated Circuits (3D ICs) Application

Huang,

Lin,

Hsiung

et al. 2023

Nanomaterials

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Advanced packaging technology has become more and more important in the semiconductor industry because of the benefits of higher I/O density compared to conventional soldering technology. In advanced packaging technology, copper–copper (Cu-Cu) bonding has become the preferred choice due to its excellent electrical and thermal properties. However, one of the major challenges of Cu-Cu bonding is the high thermal budget of the bonding process caused by Cu oxidation, which can result in wafer warpage and other back-end-of-line process issues in some cases. Thus, for specific applications, reducing the thermal budget and preventing Cu oxidation are important considerations in low-temperature hybrid bonding processes. This paper first reviews the advancements in low-temperature Cu-based bonding technologies for advanced packaging. Various low-temperature Cu-Cu bonding techniques such as surface pretreatment, surface activation, structure modification, and orientation control have been proposed and investigated. To overcome coplanarity issues of Cu pillars and insufficient gaps for filling, low-temperature Cu-Cu bonding used, but it is still challenging in fine-pitch applications. Therefore, low-temperature Cu/SiO2, Cu/SiCN, and Cu/polymer hybrid bonding have been developed for advanced packaging applications. Furthermore, we present a novel hybrid bonding scheme for metal/polymer interfaces that achieves good flatness and an excellent bonding interface without the need for the chemical mechanical polishing (CMP) process.

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Room-temperature bonding strategy by ultra-high isostatic pressing for a heterogeneous interconnection architecture

Guo

Man

et al. 2022

J Mater Sci: Mater Electron

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Simplified low-temperature wafer-level hybrid bonding using pillar bump and photosensitive adhesive for three-dimensional integrated circuit integration

Cited by 7 publications

References 14 publications

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

Cu-Based Thermocompression Bonding and Cu/Dielectric Hybrid Bonding for Three-Dimensional Integrated Circuits (3D ICs) Application

Room-temperature bonding strategy by ultra-high isostatic pressing for a heterogeneous interconnection architecture

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