SimpleScalar: an infrastructure for computer system modeling

Austin, Todd; Larson, Eric; Ernst, Daniel

doi:10.1109/2.982917

Cited by 1,280 publications

(700 citation statements)

References 5 publications

(2 reference statements)

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“…We can see that the IPS of MGSim is approximately 100 KIPS, and the IPS of One-IPC HLSim is approximately 1MIPS. Different simulators used in industry and academia with their simulation speed in terms of IPS are; COTSon [1] executes at 750KIPS, SimpleScalar [2] executes at 150KIPS, Interval simulator [5] executes at 350KIPS and Sesame [8] executes at 300KIPS. and MGSim [4] executes at 100KIPS.…”

Section: E Ips -Simulation Speedmentioning

confidence: 99%

High-level simulation of concurrency operations in microthreaded many-core architectures

Uddin¹

2015

GSTF J Comput

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Abstract-Computer architects are always interested in analyzing the complex interactions amongst the dynamically allocated resources. Generally a detailed simulator with a cycle-accurate simulation of the execution time is used. However, the cycleaccurate simulator can execute at the rate of 100K instructions per second, divided over the number of simulated cores. This means that the evaluation of a complex application with complex concurrency interactions on contemporary multi-core machine can be very slow. To perform efficient design space exploration we present a co-simulation environment, where the detailed execution of concurrency instructions in the pipeline of microthreaded cores and the interactions amongst the hardware components are abstracted. We present the evaluation of the high-level simulation framework against the cycle-accurate simulation framework. The results show that high-level simulator is faster and less complicated than cycle-accurate simulator and has reasonable accuracy.

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Section: E Ips -Simulation Speedmentioning

confidence: 99%

High-level simulation of concurrency operations in microthreaded many-core architectures

Uddin¹

2015

GSTF J Comput

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“…Simple Scalar SimpleScalar [9], [10] is a virtual CPU evaluation tool in cycle level on Linux based platform. 'Virtual' means it does not evaluate the actual processor conducts, but emulates a specific processor by C code.…”

Section: Power Simulatorsmentioning

confidence: 99%

Reducing Engergy Consumption in Programs Using Cohesion Technique

Ia-Manee¹,

Sophatsathit²

2013

IJCTE

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Abstract-The objective of this work is to reduce energy consumption of source programs written in C. The underlying technique employs code transformation which focuses on cohesion. Four classes of transformations will be considered: function, loop optimization, control structure, and operator. Code transformation is evaluated by effectiveness, efficiency, space complexity, number of instructions executed, number of pages, size of memory page allocated, and energy consumption. The results suggest that different cohesion level will affect the energy consumption. Moreover, different types of source code yield different energy consumptions based on cohesion measures.

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“…Given an application written in C, it is compiled with the Simplescalar [16] GCC. The execution of the application on the processor model is simulated with Modelsim [17], and its results are compared with the Simplescalar simulation results for functional verification of the processor design.…”

Section: Code Section With Three Basic Blocks: B(i) B(j) B(k) (A Bmentioning

confidence: 99%

Register File Customization for Embedded Multi-Threaded Pipelined Processors

Zhang¹,

Guo²,

Garg³

2013

IJCTE

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Abstract-Multi-threading pipelined processor design enables high performance of a single processor core by exploiting both thread-level and instruction-level parallelism. However, when it is applied to embedded systems, its demanding for large register file, hence high resource overhead and energy consumption, becomes a big issue. In this paper, we propose a customization approach to reduce register file by maximally utilizing each of the registers used. The experiments on several applications demonstrate that with our approach, the register file for a single thread can be reduced by about 50%, based on which the multi-threading processor can achieve high performance while at low energy consumption -with 17-28% throughput improvement and 20% energy reduction when compared to the single-threading processor design.Index Terms-Register file customization, multithread pipeline, energy-aware design.

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SimpleScalar: an infrastructure for computer system modeling

Cited by 1,280 publications

References 5 publications

High-level simulation of concurrency operations in microthreaded many-core architectures

High-level simulation of concurrency operations in microthreaded many-core architectures

Reducing Engergy Consumption in Programs Using Cohesion Technique

Register File Customization for Embedded Multi-Threaded Pipelined Processors

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