SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards

Abstract

Abstract-A programmable turbo decoder is designed to support multiple third-generation wireless communication standards. We propose a hybrid architecture of hardware and software, which has small size, low power, and high performance like hardware implementations, as well as the flexibility and programmability of software. It mainly consists of a configurable hardware soft-inputsoft-output (SISO) decoder and a 16-b single-instruction multipledata processor, which is equipped with five processing elements and special instructions customized for interleaving in order to provide interleaved data at the speed of the hardware SISO. A fast and flexible software implementation of the block interleaving algorithm is also proposed. The interleaver generation is split into two parts, preprocessing and on-the-fly generation, to reduce the timing overhead of changing the interleaver structure. We present detailed descriptions of the interleaving implementation applied to the W-CDMA and cdma2000 standard turbo codes. The decoder occupies 8.90 mm 2 in a 0.25-m CMOS with five metal layers and exhibits the maximum decoding rate of 5.48 Mb/s. Index Terms-cdma2000, parallel algorithm, turbo code, turbo interleaver, W-CDMA.

Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder

“…To make a fair comparison, we show the normalized chip area for each implementation; furthermore, for those supporting parallel interleaving address generation, the chip area is further normalized by the supported parallelism to determine an equivalent chip area for each generated interleaving address. The results in [9], [22], [37], [44] support on-the-fly interleaving address generation for HSPA+, but they do not support parallel decoding due to the lack of a memory conflict solver. The interleavers in [10], [11] are not reconfigurable because they support only one block size.…”

“…It is of great interest for mobile devices to support multiple standards. As an essential building block, multi-standard turbo decoders have been studied in the literature [10], [13], [14], [16], [18], [20], [23], [34], [37]- [39]. However, since the challenging memory conflict problem caused by the HSPA+ interleaving algorithm limits the parallelism degree of turbo decoders, none of them can meet the high throughput requirements of the recent HSPA+ extensions (336 Mbps for 3GPP Release 11 and 672 Mbps proposed for 3GPP Release 12 and up).…”

A Programmable Max‐Log‐MAP Turbo Decoder Implementation

“…For example, by applying radix-4 algorithms the decoders in [10,12] can process more than one trellis stage in one clock cycle. A slightly more flexible solution is to use monolithic accelerator, which is accompanied with a fully programmable processor like in [13,14]. However, a monolithic solution can be uneconomical if the memory banks are not shared.…”

“…On the contrary to [10,11], the proposed processor is programmable. When compared to [13,14], the applicationspecific computing resources are accessed via datapath in the proposed processor. Thus, the resources can be controlled in detail with software.…”

A Flexible UMTS-WiMax Turbo Decoder Architecture

“…2) The design of flexible architectures able to support multiple codes [7], [8], [9]. 3) The design of parallel decoders to sustain very high throughput (tens or hundreds of Mb/s), where the interleaver parallelization is particularly challenging, due to the problem of collisions in memory access [10], [11], [12].…”