SIMD performance in software based mobile video coding

Rintaluoma, Tero; Silvén, Olli

doi:10.1109/icsamos.2010.5642079

Cited by 3 publications

(2 citation statements)

References 4 publications

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“…In literature, several studies regarding the SIMD optimization of video-coding applications are available [7][8][9][10][11]. The scope driving these studies is the achievement of the maximum performance, adopting measures in order to reduce the known bottlenecks.…”

Section: Related Workmentioning

confidence: 99%

An Efficient Multi‐Core SIMD Implementation for H.264/AVC Encoder

2012

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The optimization process of a H.264/AVC encoder on three different architectures is presented. The architectures are multiand singlecore and SIMD instruction sets have different vector registers size. The need of code optimization is fundamental when addressing HD resolutions with real-time constraints. The encoder is subdivided in functional modules in order to better understand where the optimization is a key factor and to evaluate in details the performance improvement. Common issues in both partitioning a video encoder into parallel architectures and SIMD optimization are described, and author solutions are presented for all the architectures. Besides showing efficient video encoder implementations, one of the main purposes of this paper is to discuss how the characteristics of different architectures and different set of SIMD instructions can impact on the target application performance. Results about the achieved speedup are provided in order to compare the different implementations and evaluate the more suitable solutions for present and next generation video-coding algorithms.

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Section: Related Workmentioning

confidence: 99%

An Efficient Multi‐Core SIMD Implementation for H.264/AVC Encoder

2012

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“…Video encoding/decoding is improved in multiple works using NEON. These include AVS decoding up to 2.11× in [15], H.264 decoding up to 1.6× in [16], [17], and MPEG-4 encoding and decoding up to 2× in [16], [17]. The Fast Fourier Transform (FFT), a core algorithm for many audio/video and image processing applications was optimized to used SSE, AVX and NEON instructions to create an alternative implementation, SFFT in [18].…”

Section: Related Workmentioning

confidence: 99%

Use of SIMD Vector Operations to Accelerate Application Code Performance on Low-Powered ARM and Intel Platforms

Mitra

Johnston

Rendell

et al. 2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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Abstract-Augmenting a processor with special hardware that is able to apply a Single Instruction to Multiple Data (SIMD) at the same time is a cost effective way of improving processor performance. It also offers a means of improving the ratio of processor performance to power usage due to reduced and more effective data movement and intrinsically lower instruction counts.This paper considers and compares the NEON SIMD instruction set used on the ARM Cortex-A series of RISC processors with the SSE2 SIMD instruction set found on Intel platforms within the context of the Open Computer Vision (OpenCV) library. The performance obtained using compiler auto-vectorization is compared with that achieved using hand-tuning across a range of five different benchmarks and ten different hardware platforms. On the ARM platforms the hand-tuned NEON benchmarks were between 1.05× and 13.88× faster than the auto-vectorized code, while for the Intel platforms the hand-tuned SSE benchmarks were between 1.34× and 5.54× faster.

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A study of the use of SIMD instructions for two image processing algorithms

Welch

Patru

Saber

et al. 2012

2012 Western New York Image Processing Workshop

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Many media processing algorithms suffer from long execution times, which are most often not acceptable from an end user point of view. Recently, this problem has been exacerbated because media has higher resolution. One possible solution is through the use of Single Instruction Multiple Data (SIMD) architectures, such as ARM's NEON. These architectures take advantage of the parallelism in media processing algorithms by operating on multiple pieces of data with just one instruction. SIMD instructions can significantly decrease the execution time of the algorithm, but require more time to implement. This thesis studies the use of SIMD instructions on a Cortex-A8 processor with NEON SIMD coprocessor. Both image processing algorithms, bilinear interpolation and distortion, are altered to process multiple pixels or colors simultaneously using the NEON coprocessor's instruction set. The distortion algorithm is also altered at the assembly level through the removal of memory accesses and branches, adding data prefetch instructions, and interlacing ARM and NEON instructions. Altering the assembly code requires a deeper understanding of the code and more time, but allows for more control and higher speedups. The theoretical speedup for the bilinear interpolation and distortion algorithms is three and four times respectively. The actual measured speedup for the bilinear interpolation algorithm is more than two times, and for the distortion algorithm is more than three times. The results show that SIMD instructions can provide a speedup to image processing algorithms following a correct sequence of modifications of the code. v Contents Dedication .

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SIMD performance in software based mobile video coding

Cited by 3 publications

References 4 publications

An Efficient Multi‐Core SIMD Implementation for H.264/AVC Encoder

An Efficient Multi‐Core SIMD Implementation for H.264/AVC Encoder

Use of SIMD Vector Operations to Accelerate Application Code Performance on Low-Powered ARM and Intel Platforms

A study of the use of SIMD instructions for two image processing algorithms

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