SIMD extension to VLIW multicluster processors for embedded applications

Barretta, Domenico; Fornaciari, William; Sami, M.; Pau, Danilo

doi:10.1109/iccd.2002.1106823

Cited by 1 publication

(1 citation statement)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In the same context, the authors in Barretta et al [2002] present a multiclustered VLIW architecture which can be switched between ILP (InstructionLevel Parallelism) and SIMD modes. The associated compiler is expected to identify pieces of code that can be executed in SIMD mode by determining accesses to disjoint memory blocks (provided in the source code or computed automatically).…”

Section: Simd/mimdmentioning

confidence: 98%

Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis

Purnaprajna

Porrmann

Rueckert

et al. 2010

ACM Trans. Reconfigurable Technol. Syst.

View full text Add to dashboard Cite

In multiprocessors, performance improvement is typically achieved by exploring parallelism with fixed granularities, such as instruction-level, task-level, or data-level parallelism. We introduce a new reconfiguration mechanism that facilitates variations in these granularities in order to optimize resource utilization in addition to performance improvements. Our reconfigurable multiprocessor QuadroCore combines the advantages of reconfigurability and parallel processing. In this article, a unified hardware-software approach for the design of our QuadroCore is presented. This design flow is enabled via compiler-driven reconfiguration which matches application-specific characteristics to a fixed set of architectural variations. A special reconfiguration mechanism has been developed that alters the architecture within a single clock cycle.The QuadroCore has been implemented on Xilinx XC2V6000 for functional validation and on UMC's 90nm standard cell technology for performance estimation. A diverse set of applications have been mapped onto the reconfigurable multiprocessor to meet orthogonal performance characteristics in terms of time and power. Speedup measurements show a 2-11 times performance increase in comparison to a single processor. Additionally, the reconfiguration scheme has been applied to save power in data-parallel applications. Gate-level simulations have been performed to measure the power-performance trade-offs for two computationally complex applications. The power reports confirm that introducing this scheme of reconfiguration results in power savings in the range of 15-24%.

show abstract

Section: Simd/mimdmentioning

confidence: 98%