Silicon‐On‐Insulator Devices

Int J RF Microw Comput Aided Eng

2021

This article investigates the impact of the p-p + junction (at the body-substrate interface) on different direct current (DC) and analog/radio frequency (RF) performance parameters of a newly invented structure called vertical superthin body field effect transistor (VSTB FET) through a well-calibrated TCAD tool. At a fixed body doping, the influence of p-p + junction was inspected for different substrate doping (N s ); which reveals that N s has a robust control on the device electrostatics. Interestingly, higher N s is seen to significantly suppress different short channel effects (SCEs), which in turn helps to improve various DC parameters excellently. An increase in N s from 10 15 to 10 18 cm À3 improves off-state leakage current and on-to-off current ratio by three orders of magnitude. Also, such a change in N s decreases subthreshold swing and drain-induced-barrier-lowering by 8.78 mV/dec and 11.15 mV/V, respectively. The underlying physics behind such improvement at higher N s is explored through the off-state channel electron density profiles corresponding to different N s values. Further, different analog/RF parameters such as transconductance, input capacitance, gate-drain capacitance, output conductance, gain-bandwidth-product, and transconductance frequency product (TFP) show slight improvement for increasing N s . In contrast, TGF, GFP, and GTFP offer large enhancement at higher N s . This study is expected to demonstrate the significance of N s on device performance.

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The beneficial impact of a p–p ⁺ junction on DC and analog/radio frequency performance of a vertical super‐thin body FET

Int J RF Microw Comput Aided Eng

2021

“…1 To address such issue, researchers suggested various non-classical FET structures such as silicon-on-insulator (SOI) FET, FinFET etc. [2][3][4][5][6][7][8][9][10][11][12][13][14][15] Moreover, multi-gate (double-gate/tri-gate) covering to channel is a widely used technique to enhance the gate controllability in many devices (planer FET/FinFET). 8,9,12 Although, these inventions have sufficiently suppressed SCEs in sub-micron devices, each of these structures has its own constraint.…”

mentioning

confidence: 99%

“…Despite an SOI FET provides high speed, and low power consumption, the high-cost manufacturing process of this novel device restricts its mass production. [2][3][4][5][6][7] The increased gate control in a multi-gate device offers great robustness to the SCEs; however, the use of more than one gate has a detrimental impact on the carrier mobility at thin-channel devices. If multiple gates cover a thin channel (in a 2D/3D device), then in on-state the carriers flowing through it feel strong multi-directional electric fields emanating from different gates; which results in increased carrier-carrier scattering and deteriorates drain current.…”

mentioning

confidence: 99%

Silicon and Germanium Vertical Super-Thin Body (VSTB) FET: A Comparative Performance Overview Including Architectural Stress-Strain Impact

ECS J. Solid State Sci. Technol.

2022

This article aims to develop a comprehensive understanding of the comparative performance of a vertical super-thin body (VSTB) field-effect transistor in terms of two device material variations (silicon/Si and germanium/Ge) with the aid of 3-D Senaturus TCAD tool. More importantly, the influence of the inevitable architectural stress (exerted over the thin body by the thick dielectric walls) on the transfer characteristic of the device is also addressed for Si/Ge device. From the perspective of suitability in high-performance circuits, Ge outperforms Si by enhancing on-state current (Ion) by 30.28, 30.29, 29.91, and 26.98 µA at channel length of 10, 20, 30, and 40 nm, respectively, with an improvable deterioration in off-state leakage current, subthreshold swing, and drain-induced-barrier-lowering. Further, a three-dimensional stress analysis reveals that stress increases Ion more in Ge-device compared to its Si-counterpart. As expected, a similar nature is observed for the strain application. Finally, the radio-frequency study shows that although the relative performance of Ge with respect to Si in terms of input capacitance, gate-drain capacitance, and output conductance is inferior, the greater transconductance of Ge than Si lowers intrinsic delay and enhances the peaks of intrinsic gain, unit-gain cut-off frequency, and gain-bandwidth-product.

Study of enhanced DC and analog/radio frequency performance of a vertical super‐thin body FET by high‐k gate dielectrics

Int J RF Microw Comput Aided Eng

2021

This article reports the DC and analog/radio frequency (RF) response of a newly invented device called vertical super‐thin body (VSTB) FET towards high‐k (Si3N4/HfO2) and low‐k (SiO2) gate dielectrics in conjunction with the scaling effect through a well‐calibrated Sentaurus TCAD tool. At channel length (LG) of 20 nm, compared to SiO2, Si3N4 improves various DC parameters such as off‐state leakage current (Ioff), on‐current (Ion), on‐to‐off current ratio (Ion/Ioff ratio), subthreshold swing (SS), and drain‐induced‐barrier‐lowering (DIBL) by 77.15%, 26.2%, one order of magnitude, 15.78%, and 36.2%, respectively. On the other hand, a higher improvement is seen in all these DC parameters for the HfO2 gate dielectric (Ioff, Ion, Ion/Ioff ratio, SS, DIBL improves respectively by 91.8%, 41.57%, two orders of magnitude, 28.28%, and 62.71%). The underlying physics behind such excellent improvement is explained by the device off‐state energy band diagram, electrostatic potential, and channel electron density profile for each dielectric. Further, for all the gate dielectrics considered, the device characteristics were studied for a wide range of LG from 10 to 50 nm to reveal the scaling impact on the device performance. Irrespective of the gate dielectric material, the device exhibits excellent performance at LG = 10 nm, which in turn indicates to the brilliant scalability of this new device. Besides, although Si3N4 and HfO2 increase gate capacitance (Cgg)/gate‐drain capacitance (Cgd), due to the extremely low values of Cgg/Cgd, enhanced unit gain cut‐off frequency, and gain‐bandwidth‐product is achieved. In addition, the increased transconductance (gm) of the device applying Si3N4/HfO2 gate dielectric leads to a higher peak value of TGF, intrinsic gain, TFP, GFP, and GTFP. This study intends to expand the fundamental knowledge about such a new device as a VSTB FET and hence, aims to be utilized in the future research of this novel device.