Silicon nanocrystal based memory devices for NVM and DRAM applications

Rao, R. A.; Steimle, R.F.; Sadd, M.; Swift, C.T.; Hradsky, B.; Straub, S.; Merchant, T.; Stoker, M. W.; Anderson, S. G.; Rossow, M.; Yater, J.A.; Acred, B.; Harber, K.; Prinz, E.J.; White, Bruce; Muralidhar, R.

doi:10.1016/j.sse.2004.03.021

Cited by 87 publications

(52 citation statements)

References 4 publications

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“…21 For example, some of the holes may tunnel through the whole high-k stack to reach the gate electrode. 22 On the other hand, since the saturation phenomenon shown in the electron-trapping process does not occur in the hole-trapping process, the hole-trapping mechanism may be different from the electron-trapping mechanism. The details will be discussed later in the bias-dependent charge trapping process section.…”

Section: Resultsmentioning

confidence: 99%

Charge Trapping and Detrapping in nc-RuO Embedded ZrHfO High-k Thin Film for Nonvolatile Memory Applications

Lin

Kuo

2012

J. Electrochem. Soc.

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The charge trapping and detrapping characteristics of the nc-RuO embedded Zr-doped HfO 2 (ZrHfO) high-k MOS capacitor have been studied. The memory function of the capacitor is mainly contributed by hole trapping during the forward sweep from −9 V to +9 V and electron trapping during the backward sweep from +9 V to −9 V. The time-and bias-dependent stress test results show that the hole-trapping efficiency is higher than the electron-trapping efficiency due to different charge trapping sites and supply mechanisms. In order to delineate the detailed mechanisms, samples were characterized with the frequency-dependent conductancevoltage curves, relaxation currents, ramp-relax current measurements, and retention characteristics. Although most electrons are deeply trapped in the bulk nc-RuO sites, a portion of holes are loosely trapped at the nc-RuO/ZrHfO interface due to the lost of the short-term retention capability. The deeply-trapped holes and electrons were strongly held for a long period. The nanocrystals embedded high-k thin film is a potentially important gate dielectric structure for the high-density floating-gate nonvolatile memory due to the high charge storage capability, low operation power, and long retention time.1-3 Based on the same equivalent oxide thickness (EOT), the HfO 2 high-k film has a thicker physical thickness than SiO 2 . In addition, HfO 2 has lower electron and hole energy barriers with respect to Si than SiO 2 , i.e., 1.5 eV and 3.4 eV, vs. 3.5 eV and 4.3 eV, respectively. 4 Previously, it was reported that the sputter deposited Zr-doped HfO 2 (ZrHfO) film showed a higher amorphous-to-polycrystalline crystallization temperature and better interface quality than the undoped HfO 2 .5 An ultra thin ZrHfO layer, e.g., EOT∼1 nm, was successfully prepared into a MOS capacitor. 6 Separately, it has been demonstrated that conductive materials, such as metals, indium tin oxide (ITO), or zinc oxide (ZnO), can be prepared into the nanocrystalline (nc) form and embedded in the high-k film as the electron-or hole-trapping medium.7-9 The charge trapping characteristics in this kind of device are closed related to the embedded nanocrystal material. For example, the nc-ITO embedded device prefers to trap holes while the nc-ZnO embedded device traps electrons or holes depending on the polarity of the gate voltage. 8, 9 Ruthenium oxide (RuO) is a conductive oxide with excellent diffusion barrier quality, good chemical and thermal stability, and a high work function (∼5 eV), which makes it a good deep charge trapping medium in the dielectric film.10-13 Previously, Maikap et al. 14 reported that nc-RuO could be included in the HfO 2 /Al 2 O 3 high-k film using the atomic layer deposition (ALD) method. Authors have also demonstrated that excellent memory functions were obtained with the nc-RuO embedded ZrHfO film prepared by the sputter deposition method followed by a post deposition annealing (PDA) step.15 Although the basic memory function has been demonstrated, the detailed charge trapping and retention...

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Section: Resultsmentioning

confidence: 99%

Charge Trapping and Detrapping in nc-RuO Embedded ZrHfO High-k Thin Film for Nonvolatile Memory Applications

Lin

Kuo

2012

J. Electrochem. Soc.

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“…Therefore, their height was close to the nanoparticle size. The size and spacing of dots are important parameters that affect the performance of nonvolatile memories [3,11]. Figure 3 shows the drain current-drain voltage (I ds −V d ) characteristics of the OTFTs embedded with and without nc-C dots obtained by sweeping V d from 0 to 20 V. The I ds − V d characteristics were measured before and after 10 min charge injection.…”

Section: Resultsmentioning

confidence: 99%

Carbon Nanocrystal-Based Organic Thin-Film Transistors for Nonvolatile Memory Nanodevices

Mohamad

Tada

Miura

et al. 2009

e-J. Surf. Sci. Nanotechnol.

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Organic semiconductor nonvolatile memory devices were successfully fabricated from organic thin-film transistors (OTFTs) embedded with nanocrystal carbon (nc-C) dots incorporating pentacene as an active layer. The nc-C dots were arranged in the channel region by a focused ion beam (FIB) technique using a precursor of low energy Ga + ions and a carbon source. The formation and morphology of nc-C dot arrays were investigated using a scanning ion microscopy (SIM) and atomic force microscopy (AFM), respectively. The SIM and AFM images show that the nc-C dot array was successfully grown on the SiO2 layer. The density of the two-dimensional nc-C dots was 5 × 10 9 cm −2 . The current-voltage (I − V ) characteristics at room temperature show that the fabricated OTFTs exhibit a memory effect upon the application of forward and reverse bias. Under the effect of gate bias, on and off states were induced and a threshold voltage shift (∆V th = 0.23 V) was obtained. The charge carrier mobility (µ) of the OTFTs is similar in both on and off states. The memory effect was attributed to the nc-C dots in the pentacene-dielectric interface.

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“…The insulator of such MIS structure normally consists of three layers (Dimitrakis et al, 2005;Tiwari et al, 1996;Tsoi et al, 2005): (i) ultra thin tunnel SiO 2 layer grown on the crystalline Si wafer followed by (ii) composite layer of Si nanocrystals (NCs) in a SiO 2 matrix (nc-Si-SiO 2 ) and (iii) control SiO 2 layer, which insulates the NCs from the control gate. The middle nc-Si-SiO 2 layer has been mostly prepared by ion implantation of Si in thermal SiO 2 and subsequent annealing at high temperature ( 900 0 ) (Normand et al, 2004 and references therein;Carreras et al, 2005;Ng et al, 2006a), by applying some chemical vapor deposition (CVD) technique for Si nanocrystals fabrication and subsequent CVD deposition of silicon dioxide (Lombardo et al, 2004;Oda et al, 2005;Rao et al, 2004), by deposition of a ultra thin amorphous Si layer and a subsequent oxidation of this layer at a high temperature (Kouvatsos et al, 2003;Tsoi et al, 2005) or by thermal evaporation of SiO powder under selected oxygen pressure (Lu et al, 2005(Lu et al, , 2006.…”

Section: Introductionmentioning

confidence: 99%

“…Devices for non-volatile purposes were produced using 3.8-5.0 nm thick tunnel oxide (Rao et al, 2004) and a threshold voltage shift of ~ 1.5 V has www.intechopen.com Recently tunnel barrier engineering has been suggested (Jung&Cho, 2008) as a promising way for tunnel oxide scaling. It uses multiple dielectric stacks to enhance field-sensitivity and thus to allow for shorter writing/erasing times and/or lower operating voltages than single SiO 2 tunnel oxide without altering the ten-year data retention constraint.…”

Section: Introductionmentioning

confidence: 99%

Silicon Oxide Films Containing Amorphous or Crystalline Silicon Nanodots for Device Applications

Nesheva¹,

Nedev²,

Curiel³

et al. 2012

Quantum Dots - A Variety of New Applications

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Silicon nanocrystal based memory devices for NVM and DRAM applications

Cited by 87 publications

References 4 publications

Charge Trapping and Detrapping in nc-RuO Embedded ZrHfO High-k Thin Film for Nonvolatile Memory Applications

Charge Trapping and Detrapping in nc-RuO Embedded ZrHfO High-k Thin Film for Nonvolatile Memory Applications

Carbon Nanocrystal-Based Organic Thin-Film Transistors for Nonvolatile Memory Nanodevices

Silicon Oxide Films Containing Amorphous or Crystalline Silicon Nanodots for Device Applications

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