Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm

Jindal, Ankit; Kumar, Binod; Jindal, Nitish; Fujita, Masahiro; Singh, Virendra

doi:10.1109/isvlsi.2018.00019

Cited by 4 publications

(3 citation statements)

References 7 publications

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“…We have obtained the results for two regions to different scenarios. In global signal selection, they assumed that the errors are uniformly distributed without considering active regions and error zones [Jindal, Kumar, Jindal et al (2018); Kumar, Jindal, Fujita et al (2017)] whereas the proposed technique considers error detection and restoration. After this, error-one technique has evolved and this approach was focused only on static region that considers all the regions are active.…”

Section: Methodsmentioning

confidence: 99%

“…This mechanism contains thousands of logic gates that results difficulty in debugging at the gate-level. For bug localisation, the Machine Learning Method (MLM) have been used recently ; Jindal, Kumar, Jindal et al (2018)] in both the stages of verification and validation. During testing, a large amount of information can be collected using some learning techniques like regression, clustering, etc.…”

Section: Background and Related Workmentioning

confidence: 99%

“…The contiguous algorithm determines the metric between the points (node). One such metric is Euclidean Distance (ED) that measures the dissimilarity between the two points in Jindal et al [Jindal, Kumar, Jindal et al (2018)]. The distance between the two points a and b having the line segment of .…”

Section: Figure 4: Illustrative Of Regions With Error Zonesmentioning

confidence: 99%

See 2 more Smart Citations

Region-Aware Trace Signal Selection Using Machine Learning Technique for Silicon Validation and Debug

Agalya¹,

Muthaiah²,

Muralidharan³

2019

Computer Modeling in Engineering &Amp; Sciences

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In today's modern design technology, post-silicon validation is an expensive and composite task. The major challenge involved in this method is that it has limited observability and controllability of internal signals. There will be an issue during execution how to address the useful set of signals and store it in the on-chip trace buffer. The existing approaches are restricted to particular debug setup where all the components have equivalent prominence at all the time. Practically, the verification engineers will emphasis only on useful functional regions or components. Due to some constraints like clock gating, some of the regions can be ignored during execution. Likewise, some of these regions can be verified deeply and have minimum errors compared to other control regions. The proposed system focusses on random signals that identify more errors which are prone to signal selection technique with low area overhead. To enhance the observability, a machine learning technique is developed. Based on the training samples of smaller designs, a model is developed to find out the contiguous neighbours of each flip-flop. This can eliminate the obstacles of unknown signals. This system demonstrates using Opencores and ISCAS'89 benchmark circuits that result in easy and fast error detection compared to the state-of-theart of other methods. This is also verified using gate-level error models by cross-validation of each debug run.

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Section: Methodsmentioning

confidence: 99%

Section: Background and Related Workmentioning

confidence: 99%