Silicides for 65 nm CMOS and Beyond

Abstract

An overview of silicide development for the 65 nm node and beyond is presented. The scaling behavior of Co based and Ni based silicides to sub-100 nm junctions and sub-40 nm gate lengths was investigated. Co and Co-Ni silicides required a high thermal budget to achieve low diode leakage. Even for lower thermal budgets, the sheet resistance of Co and Co-Ni silicides increased at gate lengths below 40 nm. NiSi had low sheet resistance down to 30 nm gate lengths exhibiting a reverse linewidth effect (sheet resistance decreased with decreasing linewidth), achieved lower contact resistivity than CoSi2 and lower diode leakage for similar sheet resistance values. Bridging issues cannot be ignored for NiSi, in particular for thicker Ni films, higher RTP temperatures and in the presence of Ti. Material issues for the application of NiSi were also investigated. Ni2Si was found to grow with diffusion limited kinetics in the 225-300°C range, with an activation energy of 1.5 eV. Results of the kinetic studies were used to design a two-step RTP process that limited the silicide thickness on small features by a low thermal budget first RTP step, reducing the reverse linewidth effect and avoiding excessive silicidation. In the presence of an interfacial oxide, undesired epitaxial NiSi2 pyramidal grains grew directly at temperatures as low as 310°C on p+ Si. Thermal stability of NiSi was also investigated. We found that the initial mechanism of degradation for thin NiSi films was agglomeration, with activation energies of 2.5-3 eV. The surface after agglomeration remained quite flat with alternating NiSi and exposed Si areas, while the interface roughened significantly. Thick films also degraded initially by agglomeration at low temperatures, but by transformation to NiSi2 at higher temperatures. The addition of Pt improved thermal stability of NiSi films against agglomeration. The Ni/Si-Ge reaction was also studied, finding that the addition of Ge reduced the thermal process window and resulted in a slightly higher resistivity.

Silicides and germanides for nano-CMOS applications

“…These issues were not present for NiSi [4,5,13]. The Ni-Si reaction and silicide formation did not appear to be nucleation controlled, but mainly interface or diffusion limited.…”

“…Methods to improve the nucleation density and extend the use of TiSi 2 to dimensions in the order of 100 nm were proposed and implemented, but eventually the industry transitioned to CoSi 2 [1][2][3][4]. As dimensions kept shrinking, CoSi 2 in turn showed scalability issues [4,5,8]. Fig.…”

“…Silicides have been used in self-aligned (SALICIDE) processes for several generations of complementary metal-oxide semiconductor (CMOS) devices, to reduce the sheet resistance and provide stable Ohmic contacts with low contact resistivity on gate and source/drain (S/D) areas [1][2][3][4][5][6][7][8][9][10][11][12][13]. One of the key considerations that were taken into account for SALICIDE processes through the different technology generations was the ability to silicide small structures of critical dimensions for the corresponding technology node, achieving low sheet resistance.…”

“…These silicides form easily in scaled structures. In fact, it was found that the problem is reversed for NiSi compared to Co or Ti silicides: since Ni is the main diffusing species and available to diffuse from surrounding areas, small structures can be excessively silicided with formation of thicker than desired NiSi films [4,5]. Methods to address this problem are also discussed in Section 2.…”

“…One of the main problems found for NiSi is its poor thermal stability [3][4][5][9][10][11]. Section 3 discusses the process window and thermal stability of Ni and Pt-based contact materials, including films formed by their reaction with Si, Si:Ge and Si:C. Section 4 discusses contact resistivity and Section 5 presents a brief introduction to germanides.…”