SiGe nano-heteroepitaxy on Si and SiGe nano-pillars

Abstract

In this paper, SiGe nano-heteroepitaxy on Si and SiGe nano-pillars was investigated in a 300 mm industrial reduced pressure-chemical vapour deposition tool. An integration scheme based on diblock copolymer patterning was used to fabricate nanometre-sized templates for the epitaxy of Si and SiGe nano-pillars. Results showed highly selective and uniform processes for the epitaxial growth of Si and SiGe nano-pillars. 200 nm thick SiGe layers were grown on Si and SiGe nano-pillars and characterised by atomic force microscopy, x-ray diffraction and transmission electron microscopy. Smooth SiGe surfaces and full strain relaxation were obtained in the 650 °C-700 °C range for 2D SiGe layers grown either on Si or SiGe nano-pillars.

State of the Art and Future Perspectives in Advanced CMOS Technology

“…As CMOS technology enters the 3 nm node, GAA nanosheet/nanowire becomes the most powerful competitor to replace FinFET technology because of its excellent control of SCEs [ 189 , 190 ]. As it was mentioned above, GAA devices mainly have two forms, horizontal [ 191 , 192 ] and vertical [ 46 , 193 , 194 ], and selective etching plays a very important role in these manufacturing processes. For the preparation of horizontal nanowires shown in Figure 32 , there are three main steps that require precise selective etching to prepare inner spacers and release dummy gates and nanowire channels.…”

“…An accurate release of the channel layer is a critical step for nano-transistors. For horizontal nanowires, the precision of selective etching will affect the effective gate length, and for vertical nanowires it will affect the channel diameter [ 194 ]. The above-mentioned etching techniques offer good etching selectivity, but the etching accuracy is not high enough to meet the demand of cavity etching in the inner spacer and the precision control of the diameter of the vertical nanowire preparation.…”

SiGe nano-heteroepitaxy: An investigation of the nano-template

“…Instead, the following wet cleaning sequence was used: a dip in Ozonized water followed by a dip in diluted HF and finally a wafer drying. Such a solution was more flexible than Siconi NH3/NF3-based remote plasma, which was mandatory for 35 nm pitch size masks [7].…”

“…When grown on blanket Si, a ~ 200 nm thick Si0.76Ge0.24 layer is expected to be fully compressively strained provided that the growth temperature is low enough [8]. In previous work [7] we were able to obtain smooth and fully strain relaxed Si0.76Ge0.24 layers with a thickness of only 200 nm using heteroepitaxial growth on nano-patterned SiO2 templates. SiGe epitaxial growth was carried out on a patterned substrate with nanometer-scale seed pillars.…”

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm

“…The diameter of nanowires or pillars significantly affects the performance of the device.For sensors, a small size diameter will raise sensitivity because of the higher surface-to-volume ratio [17,18]. For GAA transistors, a small channel diameter will improve gate control and reduce device leakage and power consumption [19,20]. In the conventional bottom-up vertical nanowire preparation method, the diameter of the nanowires is mainly controlled by advanced lithography technology [14,21].…”