SiGe HBT serial transmitter architecture for high speed variable bit rate intercomputer networking

Krawczyk, T.W.; Curran, Peter F.; Ernest, M.; Steidl, S.A.; Carlough, S.R.; McDonald, J. F.; Kraft, R.P.

doi:10.1049/ip-cds:20040134

Cited by 11 publications

(5 citation statements)

References 7 publications

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“…The 1-bit bit-level pipelined adder architecture derives from the architecture in [17], with two additional CLBs configured as buffers. The VCO is implemented as a feedforward interpolated VCO where its output frequency can be adjusted by the external control voltage [6]. Xilinx-6200-based benchmark for experimenting and estimating the behavior and performance.…”

Section: Discussionmentioning

confidence: 99%

“…However, CMOS cannot provide enough speed in many applications. Ultrahigh-speed systems, such as gigahertz (GHz) analog-to-digital converters (ADCs) [1], [2], equalizers [3], [4], serializers/deserializers (SerDes) [5], [6], and wideband receivers [7], require quick responses and real-time control of digital systems that operate at frequencies in the range of 10-20 GHz or beyond. In addition, in SoC design, nowadays, high-frequency DSP is preferred over analog and RF circuits due to its increased flexibility and robustness.…”

Section: Introductionmentioning

confidence: 99%

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Impact of Deep-Trench-Isolation-Sharing Techniques on Ultrahigh-Speed Digital Systems

Zhou

McDonald

2009

IEEE Trans. Circuits Syst. II

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In the past, the large area of heterojunction bipolar transistors (HBTs) in silicon germanium (SiGe) bipolar complementary metal-oxide-semiconductor (BiCMOS) processes has prevented them from being widely used in ultrahigh-speed digital systems. The consequent longer interconnects among HBTs also offset the speed advantage of HBTs. In this brief, four deep trench isolation sharing (DTIS) methods are proposed to significantly reduce the HBT layout area. The 2 × 2 HBT layout area can be reduced by 20%-42%, and large-scale HBT system layouts can be reduced by 24%-48% or even further. Two IBM 0.18-μm SiGe 7HP chips based on Xilinx 6200 digital configurable logic blocks (CLBs) and logic cells were fabricated for verification. The maximum difference between measurement and postlayout simulation is 6.1%. Compared with the traditional layout implementation, the DTIS layout improved the system speed by 22% due to shorter interconnects among HBTs.Index Terms-Deep trench isolation sharing (DTIS), heterojunction bipolar transistor (HBT), silicon germanium (SiGe), ultrahigh-speed digital systems.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Impact of Deep-Trench-Isolation-Sharing Techniques on Ultrahigh-Speed Digital Systems

Zhou

McDonald

2009

IEEE Trans. Circuits Syst. II

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“…A unique wide bandwidth VCO design has been in development at the Rensselaer Polytechnic Institute (Troy, NY, USA) [30], [32], [33]. Originally fabricated using the GaAs HBT process in [31], the design has been adapted for use with the SiGe libraries from 7HP through 9HP.…”

Section: Vco Designmentioning

confidence: 99%

High-Speed Reconfigurable Circuits for Multirate Systems in SiGe HBT Technology

et al. 2015

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| In this paper, we discuss the advantages and opportunities presented by high-speed (> 50 GHz) reconfigurable integrated circuits and how they may drive reconfigurable systems applications, such as software-defined radio, radar, and imaging. We propose silicon-germanium (SiGe) BiCMOS as an example technology that enables ultrafast reconfigurable systems and present several circuit designs based on SiGe heterojunction bipolar transistors (HBTs). We compare circuit designs between generations of IBM's SiGe process, including a recent 9HP process featuring devices with a cutoff frequency ðf T Þ of 300 GHz. We describe an architecture for an 8-b 80-Gs/s analog-to-digital converter (ADC) and a 48 Â 48 cell fieldprogrammable gate array (FPGA), which provide powerful solutions for useful functions, such as digital signal processing (DSP) and polyphase filtering. Other circuit concepts are described, including a voltage-controlled oscillator (VCO) with a tuning range of 26 GHz and a high-performance (80 Gb/s) crossbar switch, which provide utility in reconfigurable system applications. Measured results from fabricated implementations of these described systems are presented. We comment on future prospects of these systems and examine an emerging lateral bipolar device (f T ¼ 825 GHz) having 100Â less power consumption than conventional vertical HBTs.

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“…Multi-phase clocking is attractive in the design of high-speed transmitters and receivers for serial data communication because a full-rate clock is not needed. An 8-phase 5GHz feedforward interpolated VCO was used to transmit data at 20Gb/s in a serial transmitter [1]. In this paper, a PLL that has a locking range from 10GHz to 20GHz is presented.…”

Section: Introductionmentioning

confidence: 99%

A 10-20GHz Wide Locking Range Multi-Phase Generator PLL for 80Gb/s Serial Data Communication

Yim

Curran

McDonald

2006

2006 IEEE Sarnoff Symposium

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An 8-phase 20GHz PLL has been designed for a serial transceiver. The PLL has a wide locking range from 10GHz to 20GHz with a phase noise of -112dBc/Hz at 10kHz offset. The PLL uses a four-stage ring oscillator that has a wide tuning range with a feedforward interpolation topology for coarse frequency tuning and a varactor diode load capacitance variation for fine frequency tuning. The PLL is fabricated in 0.13-,um SiGe BiCMOS technology.

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SiGe HBT serial transmitter architecture for high speed variable bit rate intercomputer networking

Cited by 11 publications

References 7 publications

Impact of Deep-Trench-Isolation-Sharing Techniques on Ultrahigh-Speed Digital Systems

Impact of Deep-Trench-Isolation-Sharing Techniques on Ultrahigh-Speed Digital Systems

High-Speed Reconfigurable Circuits for Multirate Systems in SiGe HBT Technology

A 10-20GHz Wide Locking Range Multi-Phase Generator PLL for 80Gb/s Serial Data Communication

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