SiGe channels for VT control of high-k metal gate transistors for 32nm complementary metal oxide semiconductor technology and beyond

SiGe channel deposition by batch epitaxy

“…Beside cost, the control of the SiGe channel thickness is a concern for manufacturing due to the high sensitivity of V T of the PFET device to the SiGe thickness (30 mV/nm [4]). In order to assess the variability of the SiGe thickness, volume data were generated for both tool platforms, batch and single wafer tool.…”

“…Initial studies of the batch system indicated that the morphology of SiGe channels deposited in the batch and in the single wafer tool were basically matched [4]. However, with further reduction of the SiGe layer thickness due to technology requirements some differences of the morphology between both tool systems appeared.…”

“…SiGe channels have been introduced into high volume manufacturing for 32 nm and 28 nm CMOS technology using the gate-first integration of high-k metal gate (HKMG) in order to control the PFET threshold voltage (V T ) [1][2][3][4]. The manufacturing of this new epitaxial channel material is very challenging due to the high sensitivity of V T to SiGe thickness (30 mV/nm) [4] and the cost for this additional epitaxial process step.…”

“…The manufacturing of this new epitaxial channel material is very challenging due to the high sensitivity of V T to SiGe thickness (30 mV/nm) [4] and the cost for this additional epitaxial process step. In order to reduce the cost of ownership for this process step significantly, an epitaxial batch system described by Kunii et al [5] has been evaluated.…”

“…In order to reduce the cost of ownership for this process step significantly, an epitaxial batch system described by Kunii et al [5] has been evaluated. It was demonstrated that the SiGe channel deposition by batch epitaxy fulfills the technology requirements for SiGe channels and reduces the cost of ownership by a factor of 3 compared to a single wafer tool [4].…”