A novel deep submicron SiGe-on-insulator (SGOI) MOSFET with modified channel band energy for electrical performance improvement

Rahimian, Mohammad Hassan; Orouji, Ali A.; Aminbeidokhti, Amirhossein

doi:10.1016/j.cap.2012.12.005

Cited by 16 publications

(4 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This section analyses the performance of SLC, DLSC, and TLSC. The height of the Fin (H Fin ) is taken as 36 nm, and the three structures at gate length (L G ) 20 nm and supply voltage 0.7 V. The parameters are taken according to the IRDS-2021 "5 nm" node-range [21] .…”

Section: Results and Analysismentioning

confidence: 99%

“…7(a); it represents that the SLC structure has the lowest OFF current (I OFF ) and DLSC, TLSC structures have an almost equal OFF current but more than SLC. This is because the SiGe layer in DLSC and TLSC induces strain in the channel region, which enhances the diffu- , which is required for better performance of a device according to IRDS-2021 [21] . These values are obtained at V DS = 0.7 V and V GS is varied from 0 to 1 V.…”

Section: Analysis Of Digital Performance Parametersmentioning

confidence: 99%

See 1 more Smart Citation

Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

Singh,

Chaudhary,

Dewan

et al. 2023

J. Semicond.

View full text Add to dashboard Cite

This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel. For the analysis, three different channel structures are used: (a) tri-layer stack channel (TLSC) (Si–SiGe–Si), (b) double layer stack channel (DLSC) (SiGe–Si), (c) single layer channel (SLC) (Si). The I−V characteristics, subthreshold swing (SS), drain-induced barrier lowering (DIBL), threshold voltage (V t), drain current (I ON), OFF current (I OFF), and ON-OFF current ratio (I ON/I OFF) are observed for the structures at a 20 nm gate length. It is seen that TLSC provides 21.3% and 14.3% more ON current than DLSC and SLC, respectively. The paper also explores the analog and RF factors such as input transconductance (g m), output transconductance (g ds), gain (g m/g ds), transconductance generation factor (TGF), cut-off frequency (f T), maximum oscillation frequency (f max), gain frequency product (GFP) and linearity performance parameters such as second and third-order harmonics (g m2, g m3), voltage intercept points (VIP2, VIP3) and 1-dB compression points for the three structures. The results show that the TLSC has a high analog performance due to more g m and provides 16.3%, 48.4% more gain than SLC and DLSC, respectively and it also provides better linearity. All the results are obtained using the VisualTCAD tool.

show abstract

Section: Results and Analysismentioning

confidence: 99%

Section: Analysis Of Digital Performance Parametersmentioning

confidence: 99%

Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

Singh,

Chaudhary,

Dewan

et al. 2023

J. Semicond.

View full text Add to dashboard Cite

show abstract

“…This placement results in the formation of two Si-SiGe junctions and a strained lattice structure, both of which improves carrier mobility. As illustrated in equations (4) and (5) [33], the gap between energy bands (ΔE G ) and density-of-state (N V ) in valence band are changed as the Si channel is stretched. This results in the electrons having a greater effective mass, which in turn improves their mobility.…”

Section: Device Characteristicsmentioning

confidence: 99%

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

Singh,

Chaudhary,

Dewan

et al. 2024

Eng. Res. Express

View full text Add to dashboard Cite

Junctionless FinFET devices are a substitute for conventional FinFET devices due to their less short channel effects and easy manufacturing at sub 22-nm technology node. The manuscript presents an 8T-SRAM cell based on tri-gate junctionless FinFET technology. The FinFET device is designed with source/drain of Si material and the channel as a stack of Si − Si0.75Ge0.25 − Si. The proposed SRAM cell structure consists of a CMOS inverter with stacked p-FinFETs, improving its performance in terms of noise margin and leakage power consumption. The manuscript investigates the variation of Static Noise Margin (SNM), leakage power dissipation and delay with supply voltage to analyze the sub-threshold operation of SRAM cell. The results reveal that the cascaded p-FinFETs minimize the leakage current owing to the stack eﬀect, resulting in improved noise margin and lower leakage power. The stacked p-FinFET devices based SRAM cell achieves 1.11x read noise margin, 1.11x hold noise margin, -1.08x write noise margin and 57.1% less leakage power compared to conventional SRAM cell at 1.0 V. However, it exhibits more delay due to increased resistance and capacitance of the cascaded transistors. The process variation analysis is also performed to investigate the SNM distribution using monte-carlo simulation by taking 10,000 samples. The results indicate that the SRAM cell structures provide higher than 6σ yield at range of supply voltages.

show abstract

“…The leakage current suppresses by increasing the potential barrier in the source side but it causes the on current reduction. On the other hand, the on current increases by the increment of slope of conduction/valance band and creating a built-in electric field in the channel [15]. Therefore, the key idea of this work is to amend the conduction/valence band energy by a vertical graded Ge composition in the channel.…”

Section: Introductionmentioning

confidence: 96%

A SiGe on insulator MOSFET to improve the electrical performances: Amended channel band energy

Orouji

Mohtasham

Jam

2015

Materials Science in Semiconductor Processing

Self Cite

View full text Add to dashboard Cite

A novel deep submicron SiGe-on-insulator (SGOI) MOSFET with modified channel band energy for electrical performance improvement

Cited by 16 publications

References 26 publications

Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

A SiGe on insulator MOSFET to improve the electrical performances: Amended channel band energy

Contact Info

Product

Resources

About