SIES: A Novel Implementation of Spiking Convolutional Neural Network Inference Engine on Field-Programmable Gate Array

Wang, Shuquan; Wang, Lei; Deng, Yu; Yang, Zhengjian; Guo, Shasha; Kang, Ziyang; Guo, Yufeng; Xu, Weiya

doi:10.1007/s11390-020-9686-z

Cited by 22 publications

(21 citation statements)

References 31 publications

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Section: Resultsmentioning

confidence: 99%

“…The work in [33] also surpasses our work in terms of the MNIST recognition accuracy, but at a much lower frame rate of only 164 fps. The work in [30] achieved the highest accuracy among all the works, yet without reporting their power consumption and frame rate. The architecture proposed in this paper allows for implementation of large-scale SCNN and presents competitive results in terms of the recognition accuracy and frame rate.…”

Section: Comparsion and Discussionmentioning

confidence: 97%

“…A systolic SCNN inference engine is proposed in [ 29 ], and two CONV layers with one FC layer are instantiated. A SNN inference engine called SIES is proposed in [ 30 ]and uses 2-D systolic array to accelerate the computation of the CONV layer.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps

Zhang

Yang

Shi

et al. 2021

Sensors

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Neuromorphic hardware systems have been gaining ever-increasing focus in many embedded applications as they use a brain-inspired, energy-efficient spiking neural network (SNN) model that closely mimics the human cortex mechanism by communicating and processing sensory information via spatiotemporally sparse spikes. In this paper, we fully leverage the characteristics of spiking convolution neural network (SCNN), and propose a scalable, cost-efficient, and high-speed VLSI architecture to accelerate deep SCNN inference for real-time low-cost embedded scenarios. We leverage the snapshot of binary spike maps at each time-step, to decompose the SCNN operations into a series of regular and simple time-step CNN-like processing to reduce hardware resource consumption. Moreover, our hardware architecture achieves high throughput by employing a pixel stream processing mechanism and fine-grained data pipelines. Our Zynq-7045 FPGA prototype reached a high processing speed of 1250 frames/s and high recognition accuracies on the MNIST and Fashion-MNIST image datasets, demonstrating the plausibility of our SCNN hardware architecture for many embedded applications.

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Section: Resultsmentioning

confidence: 99%

Section: Comparsion and Discussionmentioning

confidence: 97%

See 1 more Smart Citation

A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps

Zhang

Yang

Shi

et al. 2021

Sensors

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show abstract

“…Wang et al [18] propose SIES, an FPGA-based accelerator with a 2D systolic array for efficiently calculating convolutions. The core idea of systolic arrays is to read data from memory once, but reuse it in multiple PEs so that less memory accesses are required.…”

Section: Convolutional Snnsmentioning

confidence: 99%

“…These methods are primarily: convolutional layers and pooling layers. To accelerate such Convolutional Spiking Neural Networks (CSNNs) using specialized hardware, most authors propose large spatial arrays of Processing Elements (PEs) [9], [18], [19]. Spatial architectures couple PEs in such away that they can exchange intermediate results without having to access a central memory [5].…”

Section: Introductionmentioning

confidence: 99%

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks

Sommer¹,

Özkan²,

Keszöcze³

et al. 2022

Preprint

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Spiking Neural Networks (SNNs) compute in an event-based matter to achieve a more efficient computation than standard Neural Networks. In SNNs, neuronal outputs (i.e. activations) are not encoded with real-valued activations but with sequences of binary spikes. The motivation of using SNNs over conventional neural networks is rooted in the special computational aspects of spike based processing, especially the very high degree of sparsity of neural output activations. Well established architectures for conventional Convolutional Neural Networks (CNNs) feature large spatial arrays of Processing Elements (PEs) that remain highly underutilized in the face of activation sparsity. We propose a novel architecture that is optimized for the processing of Convolutional SNNs (CSNNs) that feature a high degree of activation sparsity. In our architecture, the main strategy is to use less but highly utilized PEs. The PE array used to perform the convolution is only as large as the kernel size, allowing all PEs to be active as long as there are spikes to process. This constant flow of spikes is ensured by compressing the feature maps (i.e. the activations) into queues that can then be processed spike by spike. This compression is performed in runtime using dedicated circuitry, leading to a self-timed scheduling. This allows the processing time to scale directly with the number of spikes. A novel memory organization scheme called memory interlacing is used to efficiently store and retrieve the membrane potentials of the individual neurons using multiple small parallel on-chip RAMs. Each RAM is hardwired to its PE, reducing switching circuitry and allowing RAMs to be located in close proximity to the respective PE. We implemented the proposed architecture on an FPGA and achieved a significant speedup compared to other implementations while needing less hardware resources and maintaining a lower energy consumption.

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Intelligent Reasoning Engine Based on Legal Framework Network Database

Tao

Zhang

2022

Application of Intelligent Systems in Multi-Modal Information Analytics

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SIES: A Novel Implementation of Spiking Convolutional Neural Network Inference Engine on Field-Programmable Gate Array

Cited by 22 publications

References 31 publications

A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps

A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks

Intelligent Reasoning Engine Based on Legal Framework Network Database

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