Sidegating reduction for GaAs integrated circuits by using a new buffer layer

Smith, F. W.; Chen, C.L.; Turner, G. W.; Finn, M. C.; Mahoney, L.J.; Manfra, Michael J.; Calawa, A. R.

doi:10.1109/iedm.1988.32941

Cited by 12 publications

(3 citation statements)

References 9 publications

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“…It has been demonstrated that these characteristics can be obtained using lattice matched materials grown at temperatures substantially below those of normal growth conditions in which excess As in quantities of 1-2% are present. This growth regime is often referred to as Low Temperature (LT) growth [3][4][5][6]. There is, however, an intermediate growth regime between that of normal growth (500 to 600'C) and LT growth (below 200'C) in which there is little to no excess As, but in which the movement of dopant atoms has been significantly reduced, compared with material grown at normal temperature [7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

“…53 As lattice matched to InP are extremely useful for high-speed electronic and optical devices [1][2]. Device applications often require high resistivity, low lifetime material to act as buffers for electrical isolation and reduction of backgating and sidegating [3][4][5][6]. It has been demonstrated that these characteristics can be obtained using lattice matched materials grown at temperatures substantially below those of normal growth conditions in which excess As in quantities of 1-2% are present.…”

Section: Introductionmentioning

confidence: 99%

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The Use of Low Temperature AlInAs and GalnAs Lattice Matched to InP in the Fabrication of HBTs and HEMTs

et al. 1991

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AllnAs and GalnAs lattice matched to InP and grown by MBE over a temperature range of 200 to 350*C (normal growth temperature of 500'C) has been used to enhance the device performance of inverted (where the donor layer lies below the channel) High Electron Mobility Transistors (HEMTs) and Heterojunction Bipolar Transistors (HBTs), respectively. We will show that an AlInAs spacer grown over a temperature range of 300 to 350'C and inserted between the AlInAs donor layer and GaInAs channel significantly reduces Si movement from the donor layer into the channel. This produces an inverted HEMT with a channel charge of 3.0x1012 cm-2 and mobility of 9131 cm 2 /V-s, as compared to the same HEMT with a spacer grown at 500 *C resulting in a channel charge of 2.3x1012 cm-2 and mobility of 4655 cm 2 /V-s. We will also show that a GaInAs spacer grown over a temperature range of 300 to 350*C and inserted between the AlInAs emitter and GalnAs base of an npn HBT significantly reduces Be movement from the base into the emitter, thereby allowing higher Be base dopings (up to Ix10 20 cm-3

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The Use of Low Temperature AlInAs and GalnAs Lattice Matched to InP in the Fabrication of HBTs and HEMTs

et al. 1991

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“…Since then LT GaAs layers have gained a big interest because of their technological importance as buffer layers for GaAs integrated circuits. It has been shown that LT GaAs is As rich with about 1% more As than Ga [1]. Such an (413) off-stoichiometry should cause high concentration of defects.…”

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confidence: 99%

FFirst TSC and DLTS Measurements of Low Temperature GaAs

et al. 1991

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The first thermally stimulated current (TSC) and deep 1evel transient spectroscopy (DLTS) studies performed on GaAs grown by molecular beam epitaxy (MBE) at low substrate temperatures (LT GaAs) are reported. TSC experiments, conducted on as grown and 400-580°C annealed layers showed domination of arsenic antisite (EL2-like) defect and supported its key role in hopping conductivity. DLTS studies, performed on Si doped and annealed at 800°Clayers revealed substantially lower concentration of EL2-like defect and an electron trap of activation energy ΔE = 0.38 eV was found. The growth of GaAs by molecular beam epitaxy (MBE) at low (190-250°C) substrate temperatures (further referred to as LT GaAs layers) started three years ago. Since then LT GaAs layers have gained a big interest because of their technological importance as buffer layers for GaAs integrated circuits. It has been shown that LT GaAs is As rich with about 1% more As than Ga [1]. Such an (413)

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Compound Semiconductor Device Processing

Parsey

2013

Materials Science and Technology

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The sections in this article are Introduction Doping Processes Ion Implantation Diffusion Methods Epitaxial Methods Isolation Methods Mesa Etching Ion Implantation Isolation Sidegating and Backgating Diffusion Etching Techniques Wet Etching Dry Etching Ohmic Contacts Schottky Barriers and Gates Annealing Dielectrics and Interlayer Isolation Resistors Metallization and Liftoff Processes Metallization Liftoff Processes Backside Processing and Die Separation Backside Processing Die Separation

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Sidegating reduction for GaAs integrated circuits by using a new buffer layer

Cited by 12 publications

References 9 publications

The Use of Low Temperature AlInAs and GalnAs Lattice Matched to InP in the Fabrication of HBTs and HEMTs

The Use of Low Temperature AlInAs and GalnAs Lattice Matched to InP in the Fabrication of HBTs and HEMTs

FFirst TSC and DLTS Measurements of Low Temperature GaAs

Compound Semiconductor Device Processing

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