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2012 39th Annual International Symposium on Computer Architecture (ISCA) 2012
DOI: 10.1109/isca.2012.6237010
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Side-channel vulnerability factor: A metric for measuring information leakage

Abstract: There have been many attacks that exploit side-effects of program execution to expose secret information and many proposed countermeasures to protect against these attacks. However there is currently no systematic, holistic methodology for understanding information leakage. As a result, it is not well known how design decisions affect information leakage or the vulnerability of systems to side-channel attacks.In this paper, we propose a metric for measuring information leakage called the Side-channel Vulnerabi… Show more

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Cited by 60 publications
(108 citation statements)
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“…In particular, existing schemes no longer retain security if the adversary can additionally observe which cache-lines are accessed within the cache (i.e., when no cache miss occurs). In other words, known external-memory oblivious algorithms [33,32,35] are vulnerable to a well-known cache-timing attack [53,21,68,67] that arises due to the timesharing of on-chip caches among multiple processes. Specifically, an adversary who controls a piece of software co-resident on the same machine as the victim application, can selectively evict the victim application's cache-lines and thus infer which cachelines the victim application is requesting through careful timing measurements.…”
Section: Our Results and Contributionsmentioning
confidence: 99%
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“…In particular, existing schemes no longer retain security if the adversary can additionally observe which cache-lines are accessed within the cache (i.e., when no cache miss occurs). In other words, known external-memory oblivious algorithms [33,32,35] are vulnerable to a well-known cache-timing attack [53,21,68,67] that arises due to the timesharing of on-chip caches among multiple processes. Specifically, an adversary who controls a piece of software co-resident on the same machine as the victim application, can selectively evict the victim application's cache-lines and thus infer which cachelines the victim application is requesting through careful timing measurements.…”
Section: Our Results and Contributionsmentioning
confidence: 99%
“…Since the mainstream commodity processors (even secure processors such as Intel's SGX) allow multiple processes or multiple virtual machines to time-share the same on-chip cache, a well-known cache-timing attack is possible where a malicious process (or virtual machine respectively) co-resides on the same physical machine as the victim process (or virtual machine respectively) can learn the victim process's internal secrets such as decryption keys [53,21,68,67]. In such a cache-timing attack, the attacker process selectively evicts a subset of the victim process's cache-lines from the shared cache.…”
Section: Practical Motivation and Justification Of Our Modelmentioning
confidence: 99%
“…7. For the results presented in this appendix, we used the same set of simulations as detailed in the original SVF paper [5], though we only use the "in order" attackers on SMT-enabled systems with the Timewarp microarchitectural protection.…”
Section: Resultsmentioning
confidence: 99%
“…As in the SVF paper [5], we present results in the form of a cumulative histogram, allowing us to quickly look at many configurations 3 . In Figure 7 we examine SMT systems at a fine granularity of 10,000 victim instructions.…”
Section: Resultsmentioning
confidence: 99%
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