TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks

Abstract

Over the past two decades, several microarchitectural side channels have been exploited to create sophisticated security attacks. Solutions to this problem have mainly focused on fixing the source of leaks either by limiting the flow of information through the side channel by modifying hardware, or by refactoring vulnerable software to protect sensitive data from leaking. These solutions are reactive and not preventative: while the modifications may protect against a single attack, they do nothing to prevent future side channel attacks that exploit other microarchitectural side channels or exploit the same side channel in a novel way.In this paper we present a general mitigation strategy that focuses on the infrastructure used to measure side channel leaks rather than the source of leaks, and thus applies to all known and unknown microarchitectural side channel leaks. Our approach is to limit the fidelity of fine grain timekeeping and performance counters, making it difficult for an attacker to distinguish between different microarchitectural events, thus thwarting attacks. We demonstrate the strength of our proposed security modifications, and validate that our changes do not break existing software. Our proposed changes require minor -or in some cases, no -hardware modifications and do not result in any substantial performance degradation, yet offer the most comprehensive protection against microarchitectural side channels to date.

Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs

“…First, using ideas similar to those presented in [2] and [20], we split program execution into coarse-grain time epochs. Second, we architect the secure processor with learning mechanisms that choose a new ORAM rate out of a set of allowed rates only at the end of each epoch.…”

“…If the adversary and secure processor share main memory (e.g., a DRAM DIMM), a straightforward way to measure ORAM access frequency is for the adversary to measure its own average DRAM access latency (e.g., use performance counters to measure resource contention [20,35]). …”

“…We cannot list all relevant articles, but two related papers are Time Warp [20] and Wang et al [35]. Time Warp also uses epochs to fuzz architectural mechanisms (e.g., the RDTSC instruction) and, using statistical arguments, decrease timing leakage.…”

Securing the Cloud: Threats, Attacks and Mitigation Techniques

“…Papers such as [37] discussed mitigating side-channel attacks in different environments. This paper proposed a general mitigation strategy that focuses on the infrastructure used to measure side channel leaks rather than the source of leaks.…”

Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller

“…Note that techniques such as cache partitioning can isolate the cache activity of one thread from another, but it does not eliminate the memory timing channels, i.e., memory latencies of one thread are impacted by the cache miss rate of the co-scheduled thread. Martin et al [13] thwart timing channel attacks by limiting a user's ability to take fine-grained timing measurements. Saltaformaggio et al [22] identify potential attacks because of atomic instructions that can lock up the entire memory system; they develop solutions that require hypervisor extensions.…”