Side-Channel Masking with Pseudo-Random Generator

Abstract

High-order masking countermeasures against side-channel attacks usually require plenty of randomness during their execution. For security against t probes, the classical ISW countermeasure requires O(t 2 s) random bits, where s is the circuit size. However running a True Random Number Generator (TRNG) can be costly in practice and become a bottleneck on embedded devices. In [IKL + 13] the authors introduced the notion of robust pseudo-random number generator (PRG), which must remain secure even against an adversary who can probe at most t wires. They showed that when embedding a robust PRG within a private circuit, the number of random bits can be reduced to Õ(t 4 ), that is independent of the circuit size s (up to a logarithmic factor). Using bipartite expander graphs, this can be further reduced to O(t 3+ε ); however the resulting construction is impractical. In this paper we describe a construction where the number of random bits is only Õ(t 2 ) for security against t probes, without expander graphs; moreover the running time of each pseudo-random generation goes down from Õ(t 4 ) to Õ(t). Our technique consists in using multiple independent PRGs instead of a single one. We show that for ISW circuits, the robustness property of the PRG is not required anymore, which leads to simple and efficient constructions. For example, for AES we only need 48 bytes of randomness to get second-order security (t = 2), instead of 2880 in the original Rivain-Prouff countermeasure. As a first feasibility result, we have implemented our countermeasure on an ARM-based embedded device with a relatively slow TRNG, and obtained a 50% speed-up compared to Rivain-Prouff.

Improved Masking Multiplication with PRGs and Its Application to Arithmetic Addition

“…Coron et al [6] proposed a special technique called locality of randomness subset, allowing the usage of multiple PRGs to reduce the randomness cost by setting proper randomness subsets of each gadget. According to it, if all gadgets are SNI-R/PINI-R defined in [6], we can securely use d-wise PRGs [7] to generate the random bit for the gadgets and keep an equivalent security in the probing model, even if the worst case where the adversary can get the variables in a PRG with one probe happens. Then, we can reuse the random seeds of dwise PRGs in different gadgets based on the locality of the subsets, which significantly reduces the randomness cost.…”

“…Then, we can reuse the random seeds of dwise PRGs in different gadgets based on the locality of the subsets, which significantly reduces the randomness cost. In [6], the ISWAND [8] has been proved as SNI-R with 1-local use of dðd þ 1Þ=2 subsets. Furthermore, two better SNI-R AND algorithms are given in [6] with d 1-local use subsets and d 2-local use subsets.…”

“…In [6], the ISWAND [8] has been proved as SNI-R with 1-local use of dðd þ 1Þ=2 subsets. Furthermore, two better SNI-R AND algorithms are given in [6] with d 1-local use subsets and d 2-local use subsets.…”

“…Our Contributions. Following [6], our main contribution is to propose a new security notion allowing multiple PRGs, and a more efficient masked d-order AND algorithm with 1local use of 2d randomness subsets based on [5] which satisfies the new notion. Besides, we consolidate the work on masked arithmetic addition by improving the existing work of Coron et al [20].…”

Efficient Private Circuits with Precomputation

“…An improved scheme that can save the RAM overhead by a factor of 2 is given in [CRZ18]. At CHES 2021, Valiveti et al [VV21] proposed a method that can reduce the RAM size to 2 k+1 k + O k k(d + 1) 2 bits by applying the technique of masking with pseudorandom generators (PRGs) [CGZ20]. However, the complexity of online-computation of this method grows to Õ( d 2 ), due to the running of PRGs.…”