Efficient Private Circuits with Precomputation

Abstract

At CHES 2022, Wang et al. described a new paradigm for masked implementations using private circuits, where most intermediates can be precomputed before the input shares are accessed, significantly accelerating the online execution of masked functions. However, the masking scheme they proposed mainly featured (and was designed for) the cost amortization, leaving its (limited) suitability in the above precomputation-based paradigm just as a bonus. This paper aims to provide an efficient, reliable, easy-to-use, and precomputation-compatible masking scheme. We propose a new masked multiplication over the finite field Fq suitable for the precomputation, and prove its security in the composable notion called Probing-Isolating Non-Inference (PINI). Particularly, the operations (e.g., AND and XOR) in the binary field can be achieved by assigning q = 2, allowing the bitsliced implementation that has been shown to be quite efficient for the software implementations. The new masking scheme is applied to leverage the masking of AES and SKINNY block ciphers on ARM Cortex M architecture. The performance results show that the new scheme contributes to a significant speed-up compared with the state-of-the-art implementations. For SKINNY with block size 64, the speed and RAM requirement can be significantly improved (saving around 45% cycles in the online-computation and 60% RAM space for precomputed values) from AES-128, thanks to its smaller number of AND gates. Besides the security proof by hand, we provide formal verifications for the multiplication and T-test evaluations for the masked implementations of AES and SKINNY. Because of the structure of the new masked multiplication, our formal verification can be performed for security orders up to 16.

Improved Masking Multiplication with PRGs and Its Application to Arithmetic Addition

“…To validate the impact of the randomness on the practical security, we run LatinAND and another multiplication gadget proposed in [28] on a ChipWhisperer STM32F4 UFO target board and collect its power traces with Picoscope 5244D at sampling rate of 125 MS/s. Besides, we perform a Welch's T-test with 10, 000 executions, whose randoms are generated by PRGs (LatinAND) and TRNGs (AND gadget proposed in [28]), respectively, to compare the randomness of the PRG implementation and the TRNG ones. Figure 4 depicts the T-test results for LatinAND, and we provide in Figure 5, the result for the other gadget with the randomness from TRNGs.…”