SiC Planar MOSFETs With Built-In Reverse MOS-Channel Diode for Enhanced Performance

Abstract

In this paper, the SiC planar MOSFET with built-in reverse MOS-channel diode (SiC MCD-MOSFET) is investigated utilizing TCAD simulation tools. When the device is working as a freewheeling diode, the operation of the parasitic body diode is suppressed effectively due to the lower threshold voltage of the MCD. Therefore, the bipolar degradation issue can be completely solved. In addition, the SiC MCD-MOSFET is featuring superior dynamic characteristics. The input capacitance (CISS), reverse transfer capacitance (C RSS), gate charge (Q G) and gate-to-drain charge (Q GD) are reduced by a factor of ~2, ~7, ~2 and ~10, respectively, as compared to the conventional SiC MOSFET (SiC C-MOSFET). Combined with the slightly increased on-resistance (R ON), tremendously enhanced figures of merit (R ON ×Q G and R ON ×Q GD are decreased by a factor of 1.8 and 9, respectively) are obtained in the SiC MCD-MOSFET. The outstanding performance and easy-to-implement feature make the SiC MCD-MOSFET more attractive for further power electronic applications. Index Terms SiC planar MOSFETs, bipolar degradation, dynamic performance.

A Novel MOS-Channel Diode Embedded in a SiC Superjunction MOSFET for Enhanced Switching Performance and Superior Short Circuit Ruggedness

“…Figure 1 represents the schematic cross-sectional views and dimension parameters of the SJ-MOSFET and MCD SJ-MOSFET. The doping and dimension parameters of the two devices refer to published work [20]. Both devices feature the same doping and dimension parameters, except for the gate structure.…”

“…Parameter SJ-MCD- The proposed device could be fabricated in a similar way compared to the SJ-MOSFET. Only one additional mask is required to form the stepped oxide, and the separation of the dummy gate and the active gate can be performed simultaneously in the subsequent etching process after N+ polysilicon deposition [17,20]. Additionally, the source contact hole etching process of the dummy gate can be performed simultaneously in the ohmic contact hole etching process.…”

“…The oxide thickness of the MCD is reduced in order to achieve a desired turn-on voltage (V F ), so as to suppress the minority carrier injection from the PIN diode. In addition, some studies adopting the MCD concept in SiC MOSFETs have been conducted [19,20]. However, the thinned oxide layer of MCD increases the maximum oxide electric field (E MOX ) to nearly 4 MV/cm, which may result in oxide breakdown or shorten the lifespan of SiC MOSFETs.…”

Numerical demonstration of SiC trench MOSFET with integrated heterojunction diode for enhanced performance

“…[10][11][12][13][14][15][16][17] The forward voltage drop (V F ) is greatly influenced by the barrier height formed between the metal and semiconductor. Another option is to split the poly gate, and one half of the cells are acted as an inversion-channel MOSchannel diode [18][19][20] or the accumulation-channel one. 21) In addition, it is also an effective measure to handle this problem by introducing a heterojunction diode (HD) into the SiC MOSFET.…”

A Novel Split-Gate-Trench MOSFET Integrated With Normal Gate and Built-In Channel Diode

“…Another solution is integrating Schottky diode but it causes larger degradations of IDS, integration level, and high temperature characteristics [14][15][16][17][18][19]. Recently, a novel technology for power MOSFET with built-in channel diode (BCD) has been proposed to solve such a problem [20][21][22][23]. O. Häberlen and his team proposed a conventional SGT MOS with BCD (CBCD-SGT) which is arranged one BCD and three normal cells alternately, as shown in Fig.…”