Si field emitter array with 90-nm-diameter gate holes

Silicon Field Emitter Arrays

“…Most recently, processes have been developed, which use oxidation-sharpened tips but remove the mask after the initial etch and form the gates using either traditional planarization techniques [37] (see Fig. 5.2) or CMP [6,38,39]. Using these methods, the gate aperture diameter can be made smaller than the original mask.…”