Shorter Field Life in Power Cycling for Organic Packages

Park, S. B.; Ahmed, Izhar Z.

doi:10.1115/1.2429706

Cited by 13 publications

(6 citation statements)

References 2 publications

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“…The parameter ξ was selected such that the constant c in equation ( 2) was less than unity, and s was then determined from the combined term s/ξ . (d) The combined constants ch o , cs o and a in equations ( 9) and (10) were determined from the constant strain rate data by a least-squares fit. The material parameters a, h o and s o were fitted from the σ ∼ ε p curves (especially the transient state) with various temperatures and strain rates [30].…”

Section: The Anand Modelmentioning

confidence: 99%

“…Since solder joints provide the mechanical and electrical interconnect between the package and the board, they are susceptible to failures during thermal cycling [9]. Temperature fluctuations caused by either power consumption or environmental changes, along with the resulting thermal expansion mismatch between the various packaging materials, result in deformation stress in packages/assemblies especially in solder interconnects [10], and accumulation of stress and strain may induce fatigue cracks in soldered joints and eventually cause the failure of the whole devices [11,12]; consequently, the reliability of the soldered joints is one of the most critical issues in electronic package development. Most reliability analysis of electronic component soldered joints require the estimation of stress-strain response using the finite element code, which needs the user to provide the constitutive relation of soldered joints for calculation accuracy.…”

mentioning

confidence: 99%

“…Most reliability analysis of electronic component soldered joints require the estimation of stress-strain response using the finite element code, which needs the user to provide the constitutive relation of soldered joints for calculation accuracy. The Anand model is a suitable unified viscoplasticity constitutive relation, widely used in the finite element simulation of solder interconnection in electronic components by many researchers [13][14][15][16][17][18][19][20]. In order to apply the Anand model to the simulation of the thermomechanical responses of the SnAgCu soldered joints with the addition of rare earth Ce in electronic packaging, the parameters of the constitutive relations must be previously determined.…”

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confidence: 99%

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Determination of Anand parameters for SnAgCuCe solder

Zhang

Xue

Gao

et al. 2009

Modelling Simul. Mater. Sci. Eng.

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A unified viscoplastic constitutive model, Anand equations, was used to represent the inelastic deformation behavior for Sn3.8Ag0.7Cu/Sn3.8Ag0.7 Cu0.03Ce solders in surface mount technology. The Anand parameters of the constitutive equations for the SnAgCu and SnAgCuCe solders were determined from separated constitutive relations and experimental results. Non-linear least-squares fitting was selected to determine the model constants. Comparisons were then made with experimental measurements of the stress–inelastic strain curves: excellent agreement was found. The model accurately predicted the overall trend of steady-state stress–strain behavior of SnAgCu and SnAgCuCe solders for the temperature ranges from −55 to 125 °C and for the strain rate range from 1% s−1 to 0.01% s−1. It is concluded that the Anand model can be applied to represent the inelastic deformation behavior of solders at high homologous temperatures and can be recommended for finite element simulation of the stress–strain response of lead-free soldered joints. Based on the Anand model, the investigations of thermo-mechanical behavior of SnAgCu and SnAgCuCe soldered joints in fine pitch quad flat package by the finite element code have been done under thermal cyclic loading, and it is found that the reliability of the SnAgCuCe soldered joints is better than that of the SnAgCu soldered joints.

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Section: The Anand Modelmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Determination of Anand parameters for SnAgCuCe solder

Zhang

Xue

Gao

et al. 2009

Modelling Simul. Mater. Sci. Eng.

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“…Moreover, the maximum accumulated plastic strain energy density per cycle ( W max ) was recommended to take the place of average plastic strain energy density accumulated per cycle ( W ave ) to evaluate the crack initiation in this study, for this approach achieves more realistic crack initiation across the solder interconnects (considering the effect of the stress or strain energy concentration) and averaging of plastic strain energy applied to predict crack initiation has a tendency to over-predict the fatigue life of solder interconnects [15]. Accordingly, the modified Dareaux' energy based method in this study can be expressed through (2) to (5),…”

Section: Substratementioning

confidence: 99%

Influence of geometry of microbump interconnects on thermal stress and fatigue life of interconnects in copper filled through silicon via structure

Yuwen

Zhou

et al. 2013

2013 14th International Conference on Electronic Packaging Technology

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Through silicon via (TSV) is an emerging technology enabling three dimensional (3D) packaging through vertical interconnection between multiple chips, which can significantly increase I/O per unit area, reduce electrical resistance as well as RC delay, and miniaturize the solder interconnects. However, it can also dramatically increase the current density and thermal energy density in each interconnect meanwhile. Thus, the reliability of miniaturized interconnects should be paid more attention. In this study, the influence of geometry of microbump interconnects, in terms of standoff height (h) and contact angle ( ), on thermal stress and fatigue life of interconnects in TSV structures under thermal cycling loading conditions was investigated by finite element (FE) method.Simulation results show that high thermal stress (herein, the equivalent stress) zones locate at Cu/Si interfaces and microbump interconnects. Considering that interconnects are the weakest part in the packaging system, their thermal stress and thermal fatigue behaviors were further investigated, and results reveal that the microbump interconnects in the lower microbump interconnect array are more vulnerable compared with that in upper arrays, and the outmost microbump interconnects in each interconnect array are most dangerous during the thermal cycling load. Furthermore, the influences of both h and on the fatigue life of the dangerous microbumps were calculated by using the modified Darveaux's energy based method. Calculation results reveal that increasing decreasing h and increasing improve the fatigue life of microbump interconnects. Besides, the thermal stress has no necessary connection with fatigue life, whereas the thermal strain (which is influenced by the thermal stress, structure factors and triaxial stress state) is closely related to the plastic strain energy and should be taken into account in evaluation of fatigue life of solder microbump interconnects in TSV structures.

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“…Thus, Anand's visco-plastic constitutive model was used for the solder bump [19]. Mechanical properties of the constitutive materials are listed in Table 1.…”

Section: Modeling and Validationmentioning

confidence: 99%

Strain behaviors of solder bump with underfill for flip chip package under thermal loading condition

Kwak

2014

J Mech Sci Technol

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Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliability challenge for flip chip packages. Revision of underfill material must be considered, which compromises the life of flip chip interconnect by releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chip package was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermomechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital image correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of cross-sectioned solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. The results clearly show captured deformations of solder bump under thermal loading. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments, and validated with experimental results. Then, consistently using the FEA analysis, parametric study for underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg), Young's modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the die side were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that high Tg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.

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Shorter Field Life in Power Cycling for Organic Packages

Cited by 13 publications

References 2 publications

Determination of Anand parameters for SnAgCuCe solder

Determination of Anand parameters for SnAgCuCe solder

Influence of geometry of microbump interconnects on thermal stress and fatigue life of interconnects in copper filled through silicon via structure

Strain behaviors of solder bump with underfill for flip chip package under thermal loading condition

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