Strain behaviors of solder bump with underfill for flip chip package under thermal loading condition

Abstract

Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliability challenge for flip chip packages. Revision of underfill material must be considered, which compromises the life of flip chip interconnect by releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chip package was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermomechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital image correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of cross-sectioned solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. The results clearly show captured deformations of solder bump under thermal loading. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments, and validated with experimental results. Then, consistently using the FEA analysis, parametric study for underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg), Young's modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the die side were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that high Tg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.

Thermally induced strain in joints with dissimilar adherends bonded with a flexible adhesive

“…The use of DIC for the inspection of joined assemblies under thermal loading has mainly focused on soldered joints in electronics packaging and assembly. In the study of Kwak et al [31] DIC was used to capture the thermo-mechanical behaviour of soldered joints, obtaining the deformations and strain development in a temperature range between 25 °C to 100°C. Tominaga et al [32] observed the thermally induced strain development between 30 °C to 230°C in bi-metal assemblies via DIC, aiming to establish a measurement system of thermal deformations in electronic packages.…”

Advanced utilization of 3D digital image correlation for thermal and impact reliabilities of electronics components

“…These days, DIC technology is also used in the electronics industry due to its robustness and high accuracy. There have been studies conducted using two-dimensional DIC technique to analyze solder joint reliability (Kwak, 2014; Yaofeng and Pang, 2008; Zhang et al , 2005). In particular, publications introducing technical implementations of 3D DIC for electronic components are increasing (Falk et al , 2019; Lim et al , 2009).…”

Experimental evaluation of neural probe's insertion induced injury based on digital image correlation method

“…Among various measuring methods, the application of microscope combined with Digital Image Correlation (DIC) has proven to be an effective experimental method. [12][13][14] By use of high-powered microscope to record the motion of speckle pattern on the material surface before and after deformation, the displacement information can be extracted by the correlation algorithm. Therefore, for the interaction between neural electrode and tissue, it can be inferred that displacement and strain field of the tissue could be obtained using this measuring method.…”