Shared-Memory Synchronization

Scott, Michael L.

doi:10.1007/978-3-031-01740-7

Cited by 31 publications

(12 citation statements)

References 194 publications

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“…Linearizability, of course, is not suitable for transactions, which must remain speculative until all operations can be made visible together. STM systems typically provide strict serializability instead: transactions in a crash-free history appear to occur in a sequential order that respects real time (if A commits before B begins, then A must serialize before B) [34,Sec. 3.1.2].…”

Section: Durable Strict Serializabilitymentioning

confidence: 99%

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Transactional Composition of Nonblocking Data Structures

Cai¹,

Wen²,

Scott³

2023

Preprint

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This paper introduces nonblocking transaction composition (NBTC), a new methodology for atomic composition of nonblocking operations on concurrent data structures. Unlike previous software transactional memory (STM) approaches, NBTC leverages the linearizability of existing nonblocking structures, reducing the number of memory accesses that must be executed together, atomically, to only one per operation in most cases (these are typically the linearizing instructions of the constituent operations).Our obstruction-free implementation of NBTC, which we call Medley, makes it easy to transform most nonblocking data structures into transactional counterparts while preserving their liveness and high concurrency.In our experiments, Medley outperforms Lock-Free Transactional Transform (LFTT), the fastest prior competing methodology, by 40-170%. The marginal overhead of Medley's transactional composition, relative to separate operations performed in succession, is roughly 2.2×.For persistent data structures, we observe that failure atomicity for transactions can be achieved "almost for free" with epoch-based periodic persistence. Toward that end, we integrate Medley with nbMontage, a general system for periodically persistent data structures. The resulting txMontage provides ACID transactions and achieves throughput up to two orders of magnitude higher than that of the OneFile persistent STM system.

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Section: Durable Strict Serializabilitymentioning

confidence: 99%

“…Most instrument each memory access and arrange to restart operations that conflict at the level of individual loads and stores. The resulting programming model is attractive, but the instrumentation typically imposes 3-10× overhead [34,Sec. 9.2.3].…”

Section: Introductionmentioning

confidence: 99%

Transactional Composition of Nonblocking Data Structures

Cai¹,

Wen²,

Scott³

2023

Preprint

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“…Both problems requires the correct synchronization of multiple computation threads sharing the same data. [5].…”

Section: A Concurrent Execution Modelsmentioning

confidence: 99%

“…The Organization of memory hierarchy such as the distribution of local and shared caches between multiple cores, types of caches and the implementation of different cache coherence protocols are the factor contributing to the multi-threaded execution performance. [3]- [5].…”

Section: B Shared-memory Synchronizationmentioning

confidence: 99%

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Shared-Semaphored Cache Implementation for Parallel Program Execution in Multi-Core Systems

Milik,

Walichiewicz

2022

International Journal of Electronics and Telecommunications

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The paper brings forward an idea of multi-threaded computation synchronization based on the shared semaphored cache in the multi-core CPUs. It is dedicated to the implementation of multi-core PLC control, embedded solution or parallel computation of models described using hardware description languages. The shared semaphored cache is implemented as guarded memory cells within a dedicated section of the cache memory that is shared by multiple cores. This enables the cores to speed up the data exchange and seamlessly synchronize the computation. The idea has been verified by creating a multi-core system model using Verilog HDL. The simulation of task synchronization methods allows for proving the benefits of shared semaphored memory cells over standard synchronization methods. The proposed idea enhances the computation in the algorithms that consist of relatively short tasks that can be processed in parallel and requires fast synchronization mechanisms to avoid data race conditions.

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Fencing Programs with Self-Invalidation and Self-Downgrade

Abdulla

Atig

Leonardsson

et al. 2016

Formal Techniques for Distributed Objects, Components, and Systems

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Cache coherence protocols using self-invalidation and selfdowngrade have recently seen increased popularity due to their simplicity, potential performance efficiency, and low energy consumption. However, such protocols result in memory instruction reordering, thus causing extra program behaviors that are often not intended by the programmer. We propose a novel formal model that captures the semantics of programs running under such protocols, and employs a set of fences that interact with the coherence layer. Using the model, we perfform a reachability analysis that can check whether a program satisfies a given safety property with the current set of fences. Based on an algorithm in [19], we describe a method for insertion of optimal sets of fences that ensure correctness of the program under such protocols. The method relies on a counter-example guided fence insertion procedure. One feature of our method is that it can handle a variety of fences (with different costs). This diversity makes optimization more difficult since one has to optimize the total cost of the inserted fences, rather than just their number. To demonstrate the strength of our approach, we have implemented a prototype and run it on a wide range of examples and benchmarks. We have also, using simulation, evaluated the performance of the resulting fenced programs.

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Shared-Memory Synchronization

Cited by 31 publications

References 194 publications

Transactional Composition of Nonblocking Data Structures

Transactional Composition of Nonblocking Data Structures

Shared-Semaphored Cache Implementation for Parallel Program Execution in Multi-Core Systems

Fencing Programs with Self-Invalidation and Self-Downgrade

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