sFtree

Bogdański, Bartosz; Reinemo, Sven-Arne; Sem-Jacobsen, Frank Olaf; Gran, Ernst Gunnar

doi:10.1145/2086696.2086734

Cited by 3 publications

(1 citation statement)

References 16 publications

(11 reference statements)

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“…It mirrors a logical tree, and there are two types of turns: UP turns (from child to parent) and DOWN turns (from parent to child). Consequently, the application of restricted turn-based routing can effectively prevent deadlock without the necessity for virtual channels [25].…”

Section: Fat-tree Topologymentioning

confidence: 99%

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

Yadav,

Ahmed,

Ambudkar

et al. 2023

MMEP

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The rapid evolution of integration technology has significantly influenced System-on-Chip (SoC) design, characterized by the unprecedented integration of numerous functional modules onto ever-shrinking chips. Consequently, facilitating robust communication between these burgeoning modules has become critical to optimizing system functionality and performance. Traditional Bus architecture, however, proves inadequate in realizing this goal. To circumvent these communication impediments, mesh and torus interconnected architectures have been proposed, with cores interconnected within a single chip using diverse routing strategies for seamless operation. This study investigates a deterministic, deadlock-free routing protocol for a modified Fat-Tree topology that incorporates a core module at the intermediate level.Utilizing the Sniper simulator environment for evaluation, it is demonstrated that the proposed protocol surpasses the X-Y routing method used in both mesh and torus topologies in terms of power efficiency and throughput. The results show a 4%-8% reduction in power consumption compared to other approaches, indicating the superior efficacy of the proposed method.

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Section: Fat-tree Topologymentioning

confidence: 99%

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

Yadav,

Ahmed,

Ambudkar

et al. 2023

MMEP

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High-Performance, Low-Complexity Deadlock Avoidance for Arbitrary Topologies/Routings

Pascual

Navaridas

2018

Proceedings of the 2018 International Conference on Supercomputing

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Recently, the use of graph-based network topologies has been proposed as an alternative to traditional networks such as tori or fattrees due to their very good topological characteristics. However they pose practical implementation challenges such as the lack of deadlock avoidance strategies. Previous proposals are either exceedingly complex, underutilise network resources or lack flexibility. We propose-and prove formally-three generic, low-complexity deadlock avoidance mechanisms that only require local information. The main strengths of our method are its topology-and routingindependence and that the virtual channel count is bounded by the length of the longest path. We evaluate our proposed mechanisms against previous proposals through an extensive simulation study to measure the impact on the performance using both synthetic and realistic traffic. First we compare against a well-known HPC mechanism for dragonfly and achieved similar performance level. Then we moved to Graph-based networks and show that our mechanisms can greatly outperform traditional, spanning-tree based mechanisms, even if these use a much larger number of virtual channels. Overall, we find that our proposal provides a simple, flexible and high performance deadlock-avoidance solution.

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C-Cell: An Efficient and Scalable Network Structure for Data Centers

Cai¹,

Li²,

Wei³

2013

JSW

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Data centers play a crucial role in current Internet architecture supporting content-centric networking. How to efficiently interconnect an exponentially increasing number of servers is a fundamental challenge in data centers networking. This paper presents C-Cell, a new network architecture which is designed on the basis of recursive structure. A high-level C-Cell is constructed by low-level C-Cell. And this structure not only has a low-ratio in switch/server, but also provides multiple parallel short paths between any pair of servers. On the premise of low proportion of switches and servers, C-Cell can efficiently achieve routing mechanisms in shorter mean path lengths with less network cost.

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sFtree

Cited by 3 publications

References 16 publications

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

High-Performance, Low-Complexity Deadlock Avoidance for Arbitrary Topologies/Routings

C-Cell: An Efficient and Scalable Network Structure for Data Centers

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