Seven Strategies for Tolerating Highly Defective Fabrication

DeHon, A.; Naeimi, Helia

doi:10.1109/mdt.2005.94

Cited by 111 publications

(52 citation statements)

References 13 publications

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“…The repair capability of defect tolerance techniques can vary greatly for different architecture designs [8]. There have been a number of promising architecture proposed for the hybrid nano/CMOS design paradigm.…”

Section: Preliminaries and Related Workmentioning

confidence: 99%

“…In a hybrid nano/CMOS architecture, unreliable but highly dense nano devices are used to provide data storage and computation while CMOS devices are utilized for interfacing and for highly critical circuit operations. It is acknowledged that due to high defect rates associated with nanotechnology, it is unlikely to compete with CMOS for general purpose computing in the near future and hence defect tolerance is necessary [5], [6], [7], [8], [9]. While defect tolerance has been addressed to some level in CMOS generation, it has gained importance recently with the emergence of novel computational paradigms that involve highly dense nano/CMOS architectures.…”

Section: Introductionmentioning

confidence: 99%

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Tagged Repair Techniques for Defect Tolerance in Hybrid Nano/CMOS Architecture

Srivastava

Melouki

Al-Hashimi

2011

IEEE Trans. Nanotechnology

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Abstract-We propose two new repair techniques for hybrid nano/CMOS computing architecture with lookup table based Boolean logic. Our proposed techniques use tagging mechanism to provide high level of defect tolerance and we present theoretical equations to predict the repair capability including an estimate of the repair cost. The repair techniques are efficient in utilization of spare units and capable of targeting upto 20% defect rates, which is higher than recently reported repair techniques.

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Section: Preliminaries and Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Tagged Repair Techniques for Defect Tolerance in Hybrid Nano/CMOS Architecture

Srivastava

Melouki

Al-Hashimi

2011

IEEE Trans. Nanotechnology

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“…The programmability also allows defective devices to be avoided as a means of fault tolerance. DeHon and Naemi have shown that when 20% of devices (i.e., crossbar diodes) were defective, only a 10% overhead in devices was needed to correctly configure the array around the defects [10]. Note that the nanoPLAs are build on top of a lithographic substrate.…”

Section: A Nanoplamentioning

confidence: 99%

Trends and Future Directions in Nano Structure Based Computing and Fabrication

Bahar

2006

2006 International Conference on Computer Design

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Abstract-As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overcome in the near future, nanoscale devices will have high manufacturing defect rates and will operate at reduced noise margins, exposing computation to higher soft error rates. Thus, a key challenge for the future will be building fault and defecttolerant computing systems. Researchers are looking to develop hybrid systems that combine on the same chip CMOS-based circuitry with any number of alternatives, including circuits composed of nanowire or carbon nanotube devices. The big advantage of including these new devices on the same chip is the increased device densities, and potential drop in fabrication costs. On the other hand, integrating very large numbers of devices on a single chip leads to questions of how to manage so many devices with tight constraints on cost, performance, power, and reliability, without having it become a design complexity nightmare. In this paper, we review some key issues and trends arising from nanostructure based computing and fabrication, while providing a few examples of defect-tolerant circuits and architectures currently being proposed as alternatives to "traditional" computing based exclusively on CMOS technology. These include hybrid nanowire/CMOS designs, reconfigurable or redundant architectures, and designs based on probabilistic computing. We end with a discussion on future challenges and direction in nanoscale computing.

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“…Config (BIST LUT with f i ); 11: if (B ) 12: while (B ) 13: Choose ((b k ,n k ) from DB) ; 22: list of functions (F) and configured on the LUT of the BIST circuit (BIST LUT, line #10). If there are available blocks in the block list (B), one of them, e.g.…”

Section: Simultaneous Configuration and Test (Sct)mentioning

confidence: 99%

“…As commonly proposed in literature, a defect detection process must be performed and location of all defects in the device must be detected and stored as a defect map and in configuration phase, defective components should be avoided [12] [13]. Several techniques have been proposed to extract the location of faulty blocks in nanoscale architectures [14][15] [22].…”

Section: Introductionmentioning

confidence: 99%