SEU-SECURE PARITY PREDICTION MULTIPLIER ON SRAM-BASED FPGAs

Abstract

Modern SRAM-based¯eld programmable gate array (FPGA) devices o®er high capability in implementing satellites and space systems. Unfortunately, these devices are extremely sensitive to various kinds of unwanted e®ects induced by space radiations especially single-event upsets (SEUs) as soft errors in con¯guration memory. To face this challenge, a variety of soft error mitigation techniques have been adopted in literature. In this paper, we describe an area-e±cient multiplier architecture based on SRAM-FPGA that provides the self-checking capability against SEU faults. The proposed design approach, which is based on parity prediction, is able to concurrently detect the SEU faults. The implementation results of the proposed architecture reveal that the average area and delay overheads are respectively 25% and 34% in comparison with the plain version while the conventional duplication with comparison (DWC) architecture imposes 117% and 22% overheads. Moreover, the single and multi-upset fault injection experiments reveal that the proposed architecture averagely provides the failure coverage of 83% and 79% while the failure coverage of the duplicated structure is 85% and 84%, respectively for SEU and MEU faults.