SEU Mitigation for Reconfigurable FPGAs

Czajkowski, David; Samudrala, P.K.; Pagey, M.P.

doi:10.1109/aero.2006.1655957

“…A very common approach currently used by the industry for SEU mitigation in FPGAs is the scrubbing technique [24,92]. Essentially scrubbing.…”

Section: Mitigation Of Transient Faults Using a Scrubbing Techniquementioning

confidence: 99%

The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

Kirischian¹

2021

Preprint

0

View full text Add to dashboard Cite

The main motivation factors for the proposed research were the increase of cost-efficiency of FPGA based systems and the simplification of the design process. The first factor is optimization of design in multi-parametric constraint space. The second factor is the design of reconfigurable systems based on higher level of abstraction in a form of macro-functions rather than conventional HDL primitives. Main goal of this work was to create a methodology for automated cost-effective design synthesis of FPGA systems by utilizing temporal partitioning concept. Temporal partitioning provides powerful mechanism that allows to design cost-effective multi-parametrically optimized architectures. Another feature of these architectures is the ability for run-time self-restoration from hardware faults. As the result of the proposed research this methodology was created and successfully verified on the first prototype of Multi-mode Adaptive Reconfigurable System (MARS) with embedded Temporal Partitioning Mechanism (TPM). A special CAD software system was developed for automated application programming, automated task segmentation, and further high-level synthesis of segment specific processors (SSPs). Several novel methodologies were proposed, developed, and verified including: a methodology for creation of macro-operators (MOs) and associated set of optimized virtual hardware components (VHCs); an automated task segmentation methodology and synthesis of segment specific processors from the VHCs; methodology for integration of fault tolerance mechanisms with the self-restoration capability. The latter mechanism made possible the mitigation of transient and permanent hardware faults in run-time. The proof-of-concept component of this research consists of implementation of the above methodologies and mechanisms in the special software CAD system and verification on the experimental setup based on the prototype of system with TPM (MARS platform). As the result, all the developed methodologies and architectural solutions were tested and their effectiveness was demonstrated.

show abstract

“…Another scrubbing technique is to use an external special processor [24,92] that runs a special SEU mitigating engine, as shown in Figure 4.l.…”

Section: Mitigation Of Transient Faults Using a Scrubbing Techniquementioning

confidence: 99%

“…In recent years there were several developments made in the field of temporal partitioning of FPGA resources. A large portion of the research [24,28,46,85] describes the analysis of task segmentation. However, not many works focused on the architecture organization of temporal partitioning mechanisms and hardware support.…”

Section: Introductionmentioning

confidence: 99%

The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

Kirischian¹

2021

Preprint

0

View full text Add to dashboard Cite

The main motivation factors for the proposed research were the increase of cost-efficiency of FPGA based systems and the simplification of the design process. The first factor is optimization of design in multi-parametric constraint space. The second factor is the design of reconfigurable systems based on higher level of abstraction in a form of macro-functions rather than conventional HDL primitives. Main goal of this work was to create a methodology for automated cost-effective design synthesis of FPGA systems by utilizing temporal partitioning concept. Temporal partitioning provides powerful mechanism that allows to design cost-effective multi-parametrically optimized architectures. Another feature of these architectures is the ability for run-time self-restoration from hardware faults. As the result of the proposed research this methodology was created and successfully verified on the first prototype of Multi-mode Adaptive Reconfigurable System (MARS) with embedded Temporal Partitioning Mechanism (TPM). A special CAD software system was developed for automated application programming, automated task segmentation, and further high-level synthesis of segment specific processors (SSPs). Several novel methodologies were proposed, developed, and verified including: a methodology for creation of macro-operators (MOs) and associated set of optimized virtual hardware components (VHCs); an automated task segmentation methodology and synthesis of segment specific processors from the VHCs; methodology for integration of fault tolerance mechanisms with the self-restoration capability. The latter mechanism made possible the mitigation of transient and permanent hardware faults in run-time. The proof-of-concept component of this research consists of implementation of the above methodologies and mechanisms in the special software CAD system and verification on the experimental setup based on the prototype of system with TPM (MARS platform). As the result, all the developed methodologies and architectural solutions were tested and their effectiveness was demonstrated.

show abstract

“…These methods also allow a certain degree of failure recovery, and they may provide solution that can heal the system itself from advanced faults. By using the strategy of redundancy, several techniques have been proposed to mitigate faults [22][23][24][25][26]. The triple modular redundancy (TMR) is one of the most commonly used methods, in which three identical functional blocks are utilized for the same functions and their outputs are checked and decided by a majority voter.…”

Section: Introductionmentioning

confidence: 99%

Optimal Partial Reconfiguration for Permanent Fault Recovery on SRAM-Based FPGAs in Space Mission

Zhang

¹

,

Guan

²

,

Mao

³

2013

Advances in Mechanical Engineering

View full text Add to dashboard Cite

In this paper, we present a technique to maximize the lifetime of SRAM-based FPGAs in space mission. We focus on recovering permanent faults induced by SEE (single-events effect). In our technique, we use a fix-sized fault detection module to detect permanent faults and propose a permanent fault recovery mechanism for fault recovery. By using partial reconfiguration, we develop a system lifetime estimation model to find the optimal partition for designing the module-based fault recovering with the maximum system lifetime. We conduct experiments with a set of real applications including SpaceWire, Wavelet, AC97, MEPG-4, 8086, and Ethernet on Xilinx XUP platforms. The experimental results show our technique can effectively improve the lifetime compared with the previous work.

show abstract

SEU Mitigation for Reconfigurable FPGAs

Abstract: This paper' ,2 discusses the application of Space (usually SRAM or Flash) that allow the user to reload their Micro's Time-Triple Modular Redundancy (TTMRTM) and designs several times. The same feature maybe be

Cited by 10 publications

References 7 publications

The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

Optimal Partial Reconfiguration for Permanent Fault Recovery on SRAM-Based FPGAs in Space Mission

Contact Info

Product

Resources

About