SEU Characterization of Three Successive Generations of COTS SRAMs at Ultralow Bias Voltage to 14.2-MeV Neutrons

Abstract

Abstract-This paper presents a SEU sensitivity characterization at ultra-low bias voltage of three generations of COTS SRAMs manufactured in 130 nm, 90 nm and 65 nm CMOS processes. For this purpose, radiation tests with 14.2 MeV neutrons were performed for SRAM power supplies ranging from 0.5 V to 3.15 V. The experimental results yielded clear evidences of the SEU sensitivity increase at very low bias voltages. These results have been cross-checked with predictions issued from the modeling tool MUlti-SCAles Single Event Phenomena Predictive Platform (MUSCA-SEP 3 ). Large-scale SELs and SEFIs, observed in the 90-nm and 130-nm SRAMs respectively, are also presented and discussed.

Evaluation of a COTS 65-nm SRAM Under 15 MeV Protons and 14 MeV Neutrons at Low VDD

“…1 shows the relationship between the bias voltage and SBUs/2-bit MCUs sensitivity for 15.6 MeV proton and 14.2 MeV neutron irradiation. The latter were obtained only with 0x55 pattern and previously presented and discussed in [4] by the authors. These were obtained in the GENEPI2 accelerator, available in Grenoble (France) [28].…”

“…Static and dynamic tests were made under 15.6 MeV protons. This allowed the authors not only validate the effects of DVS on this COTS SRAM, but also to establish a comparison with results obtained with 14.2 MeV neutrons in a previous work [4]. The parts were not delidded, and it was estimated that the encapsulation layer reduced the energy of protons on the surface of the memory to something within the range 13.4−14.2 MeV.…”

“…It is well-known that, when the bias voltage of a memory is lowered, a new problem comes up: the critical charge to trigger Single Event Upsets (SEUs) decreases [3]. In fact, recently, the authors made a characterization of the SEU sensitivity of various COTS bulk SRAMs (with 130-nm, 90-nm and 65-nm manufacturing processes) at ultra-low bias voltages under neutron irradiation that supports this point [4], [5]. SEUs fall into two classes: Single Bit Upsets (SBUs) and Multiple Bit/Cell Upsets (MBUs, MCUs).…”

“…Another one is polyethylene, typically used to protect some parts of the SEE test boards. The latter was used for the neutron experiments of [4], fairly close to the DUT (∼40-50 cm. ), which was not the case for the proton tests.…”

Impact of the Bitcell Topology on the Multiple-Cell Upsets Observed in VLSI Nanoscale SRAMs

“…In a previous work [19], the authors examined several SRAMs with 130-nm, 90-nm and 65-nm bulk CMOS manufacturing processes under 14.2 MeV neutron radiation when dynamic voltage scaling (DVS) is applied for saving power.…”