Set-Reset Flip-Flop Circuit with a Simple Output Logic

Campos-Cantón, I.; Campos-Cantón, E.; Rosu, H. C.; Castellanos-Velasco, E.

doi:10.1007/s00034-011-9343-4

Cited by 11 publications

(5 citation statements)

References 15 publications

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“…Apart from designing logic gates many efforts have been made to exploit nonlinear systems to construct memory devices. Chaos based SR flip-flop from two cross coupled Chua's circuit, SR flip-flop using reconfigurable analog block, set-reset latch in noise assisted bistable system, R-S flip-flop from two-cross coupled quasiperiodically driven MLC circuit are few examples for constructing memory latch using nonlinear systems 26,32,56,57 . In the present work, we demonstrate how the simple SC-CNN based periodically driven MLC circuit (6) can produce a consistent and complete RS flip-flop.…”

Section: Set-reset Memory Latchmentioning

confidence: 99%

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Realization of all logic gates and memory latch in the SC-CNN cell of the simple nonlinear MLC circuit

Ashokkumar,

Aravindh,

Venkatesan

et al. 2021

Preprint

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We investigate the State-Controlled Cellular Neural Network (SC-CNN) framework of Murali-Lakshmanan-Chua (MLC) circuit system subjected to two logical signals. By exploiting the attractors generated by this circuit in different regions of phase-space, we show that the nonlinear circuit is capable of producing all the logic gates, namely OR, AND, NOR, NAND, Ex-OR and Ex-NOR gates available in digital systems. Further the circuit system emulates three-input gates and Set-Reset flip-flop logic as well. Moreover, all these logical elements and flip-flop are found to be tolerant to noise. These phenomena are also experimentally demonstrated. Thus our investigation to realize all logic gates and memory latch in a nonlinear circuit system paves the way to replace or complement the existing technology with a limited number of hardware.

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Section: Set-reset Memory Latchmentioning

confidence: 99%

“…In ref. 56,57 the equation of the plane in analytical geometry has been used to build a contribution of SR flip-flop and basic logic gates 56,57 . Storni et al have investigated LSR by extending the analysis to a three well potential to realize XOR logic gates 22 .…”

Section: Introductionmentioning

confidence: 99%

Realization of all logic gates and memory latch in the SC-CNN cell of the simple nonlinear MLC circuit

Ashokkumar,

Aravindh,

Venkatesan

et al. 2021

Preprint

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“…The market of mobile phones and the field of internet of things both are increasing aggressively 1,2 . In addition to that, basic digital camera, tablet, laptop, advancement of different kinds of wearable information devices or health‐care devices are in huge demand 3,4 . These equipment are generally battery‐operated; therefore, reduction in power consumption is very crucial, in order to operate them for longer time 5,6 .…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of ultra‐low power 18T adaptive data track flip‐flop for high‐speed application

Mishra

Vaithiyanathan

Chopra

2021

Circuit Theory & Apps

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Summary This paper proposes a novel master slave (MS) flip‐flop design achieved by using only 18 transistors with a single‐phase clock and mixed topology. This design has lowest complexity, so flip‐flop basically focuses on the performance issue such as delay (TCQ) and average power consumption and compared with the other existing logic structured flip‐flops. The proposed circuit is implemented at 65‐nm Complementary Metal‐Oxide Semiconductor (CMOS), and 18‐nm finFET technology node using cadence virtuoso. The proposed flip‐flop architecture have outperformed transmission gate flip‐flop (TGFF) in terms of power (i.e., 74.52%). It is also showing improvement in terms of power as compared to 18‐transistor single‐phase clocking (18TSPC). This work also enhances the speed by reducing the delay minimum of 11.28% and PDP minimum of 37.18%. By using adaptive pass transistors topology to construct flip‐flop, the total area of the proposed flip‐flop reduces by a minimum of 4.78% with respect to 18TSPC, and also with the other flip‐flops reported in this paper. The proposed circuit can work properly within the frequency range up to 2‐GHz clock frequency. Monte Carlo simulations of Power and C to Q delay have been performed for 1000 samples.

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“…In particular, Cafagna and Grassi proposed chaos based S-R flip-flop from two cross coupled NOR gates implemented by a single Chua's circuit 16 . Campos-Canton et al 17 reported a reconfigurable analog block able to simulate different logic gates and S-R flip-flop with the logic output signal based on the equation of the plane in analytic geometry. They validated their results with experiments 17 .…”

Section: Introductionmentioning

confidence: 99%

“…Campos-Canton et al 17 reported a reconfigurable analog block able to simulate different logic gates and S-R flip-flop with the logic output signal based on the equation of the plane in analytic geometry. They validated their results with experiments 17 . Kohar and Sudeshna Sinha demonstrated how noise allows a bistable system to behave as a Set-Reset latch as well as a logic gate 11 .…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of dynamic logic gates and R-S flip-flop using quasiperiodically driven Murali-Lakshmanan-Chua circuit

Venkatesh¹,

Venkatesan²,

Lakshmanan

2017

Chaos: An Interdisciplinary Journal of Nonlinear Science

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We report the propagation of a square wave signal in a quasi-periodically driven Murali-Lakshmanan-Chua (QPDMLC) circuit system. It is observed that signal propagation is possible only above a certain threshold strength of the square wave or digital signal and all the values above the threshold amplitude are termed as 'region of signal propagation'. Then, we extend this region of signal propagation to perform various logical operations like AND/NAND/OR/NOR and hence it is also designated as the 'region of logical operation'. Based on this region, we propose implementing the dynamic logic gates, namely AND/NAND/OR/NOR, which can be decided by the asymmetrical input square waves without altering the system parameters. Further, we show that a single QPDMLC system will produce simultaneously two outputs which are complementary to each other. As a result, a single QPDMLC system yields either AND as well as NAND or OR as well as NOR gates simultaneously. Then we combine the corresponding two QPDMLC systems in a cross-coupled way and report that its dynamics mimics that of fundamental R-S flip-flop circuit. All these phenomena have been explained with analytical solutions of the circuit equations characterizing the system and finally the results are compared with the corresponding numerical and experimental analysis. Nonlinear dynamics based computing is an emerging field which can replace silicon chips and is becoming increasingly popular in nonlinear and chaotic dynamics, and computing research. Actually, Boolean based silicon chips are extremely logical in their operations. These logical operations can be classified into two groups, namely combinational logic circuits and sequential logic circuits. The basic building blocks for combinational logic circuits are the logic gates, namely AND, OR, NOT, NAND, NOR, etc., whereas the basic building block for sequential logic circuits is the flip-flop. Here, we have proposed a new mechanism by using a quasi-periodically driven nonlinear dynamical system exhibiting a strange non-chaotic attractor for constructing the logic gates AND/NAND/OR/NOR and fundamental R-S flip-flop circuit with Murali-LakshmananChua circuit as an example. By only imposing constraints on the logic high and logic low values of the input signal, we are able to implement these dynamic logic gates and flip-flop. In fact, without altering the system parameters, we point out how the logical operations can be decided by the asymmetrical input square waves. Consequently, dynamic computing using the behaviour of nona) Electronic mail: venkatesh.sprv@gmail.com b) Electronic mail: av.phys@gmail.com c) Electronic mail: lakshman@cnld.bdu.ac.in linear dynamical systems is shown to be quite implementable in hardware devices. Our results also show that nonlinearity is more significant than the existence of chaos for design of the logic gates and latches.

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Set-Reset Flip-Flop Circuit with a Simple Output Logic

Cited by 11 publications

References 15 publications

Realization of all logic gates and memory latch in the SC-CNN cell of the simple nonlinear MLC circuit

Realization of all logic gates and memory latch in the SC-CNN cell of the simple nonlinear MLC circuit

Design and analysis of ultra‐low power 18T adaptive data track flip‐flop for high‐speed application

Design and implementation of dynamic logic gates and R-S flip-flop using quasiperiodically driven Murali-Lakshmanan-Chua circuit

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