Serpentine Guard Trace to Reduce Far-end Crosstalk and Even-Odd Mode Velocity Mismatch of Microstrip Lines by More than 40%

Lee, Kyung Ho; Lee, Hyun-Bae; Jung, Hae-Kang; Sim, Jae‐Yoon; Park, Hong-June

doi:10.1109/ectc.2007.373818

Cited by 12 publications

(6 citation statements)

References 5 publications

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“…For the quantitative analysis, the difference in propagation times between the even and odd mode signals can be represented by (6) [8]: (6) where and are the propagation times of the even and odd mode signals, respectively.…”

Section: Even-odd Mode Velocity Mismatchmentioning

confidence: 99%

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A Serpentine Guard Trace to Reduce the Far-End Crosstalk Voltage and the Crosstalk Induced Timing Jitter of Parallel Microstrip Lines

Lee

Jung

et al. 2008

IEEE Trans. Adv. Packag.

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A serpentine guard trace is proposed to reduce the peak far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines on printed circuit boards. The vertical sections of the serpentine guard increase the mutual capacitance without much changing the mutual inductance between the aggressor and victim lines. This reduces the difference between the capacitive and inductive couplings and hence the far-end crosstalk. Comparison with the no guard, the conventional guard, and the via-stitch guard shows that the serpentine guard gives the smallest values in both the peak far-end crosstalk voltage and the timing jitter. The time domain reflectometer (TDR) measurement shows that the peak far-end crosstalk voltage of serpentine guard is reduced to 44% of that of no guard. The eye diagram measurement of pseudo random binary sequence (PRBS) data shows that the timing jitter is also reduced to 40% of that of no guard.

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Section: Even-odd Mode Velocity Mismatchmentioning

confidence: 99%

“…In this work, a guard trace with the serpentine form was proposed to reduce effectively both the far-end crosstalk voltage and the even-odd mode velocity mismatch of microstrip lines on PCB. The earlier version of this work was published in [6].…”

Section: Introductionmentioning

confidence: 97%

A Serpentine Guard Trace to Reduce the Far-End Crosstalk Voltage and the Crosstalk Induced Timing Jitter of Parallel Microstrip Lines

Lee

Jung

et al. 2008

IEEE Trans. Adv. Packag.

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“…Crosstalk between traces is reduced by placing Via fences [23], Serpentine Guard traces [24], Serpentine Guard trace with vias and rectangular resonators [25] in between the traces. Defective microstrip lines structures [26] have been used for the reduction of crosstalk.…”

Section: Introductionmentioning

confidence: 99%

Signal Integrity Analysis of High Speed Interconnects In PCB Embedded with EBG Structures

Sindhadevi¹,

Kanagasabai²,

Arun³

et al. 2016

Journal of Electrical Engineering and Technology

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-This paper brings out a novel method for reducing Near end and Far end Crosstalk using Electromagnetic Band Gap structures (EBG) in High Speed RF transmission lines. This work becomes useful in high speed closely spaced Printed Circuit Board (PCB) traces connected to multi core processors. By using this method, reduction of -40dB in Near-End Crosstalk (NEXT) and -60 dB in Far End Crosstalk (FEXT) is achieved. The results are validated through experimental measurements. Time domain analysis is performed to validate the signal integrity property of coupled transmission lines.

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“…The crosstalk between the multi-parallel transmission lines induces the crosstalk-induced jitter (CIJ) at receiver (RX), which is a bottleneck in increasing the transmission data rate [1][2][3][4][6][7][8]. When two signals propagate through two-coupled microstrip transmission lines, the propagation velocity of the odd mode is slightly faster than that of the static mode.…”

Section: Introductionmentioning

confidence: 99%

“…Several approaches are published to reduce crosstalk and CIJ in the multi-parallel transmission lines, by using either the line patterns in PCB [1][2][3][4][5] or the circuit techniques [6][7][8]. In [6] (the authors' prior work), the signals are sent out at transmitter (TX) at different 58times depending on the signal modes (odd, even, static), so that the signals with different modes arrive at RX at the same time.…”

Section: Introductionmentioning

confidence: 99%

A TX Clock Timing Technique for the CIJ Compensation of Coupled Microstrip Lines

Jung¹,

Lee²,

Sim³

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

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Abstract-By using the clock timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). Compared to the authors' prior work, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The delay block generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a 0.18 μm CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors' prior work, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation.

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Serpentine Guard Trace to Reduce Far-end Crosstalk and Even-Odd Mode Velocity Mismatch of Microstrip Lines by More than 40%

Cited by 12 publications

References 5 publications

A Serpentine Guard Trace to Reduce the Far-End Crosstalk Voltage and the Crosstalk Induced Timing Jitter of Parallel Microstrip Lines

A Serpentine Guard Trace to Reduce the Far-End Crosstalk Voltage and the Crosstalk Induced Timing Jitter of Parallel Microstrip Lines

Signal Integrity Analysis of High Speed Interconnects In PCB Embedded with EBG Structures

A TX Clock Timing Technique for the CIJ Compensation of Coupled Microstrip Lines

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